forked from OSchip/llvm-project
parent
3c563c5072
commit
ff62819e2f
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@ -160,6 +160,10 @@ def LDRB : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
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"ldrb $dst, [$addr]",
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[(set IntRegs:$dst, (zextloadi8 IntRegs:$addr))]>;
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def LDRB2 : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
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"ldrb $dst, [$addr]",
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[(set IntRegs:$dst, (extloadi8 IntRegs:$addr))]>;
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def LDRSB : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
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"ldrsb $dst, [$addr]",
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[(set IntRegs:$dst, (sextloadi8 IntRegs:$addr))]>;
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@ -168,6 +172,10 @@ def LDRH : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
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"ldrh $dst, [$addr]",
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[(set IntRegs:$dst, (zextloadi16 IntRegs:$addr))]>;
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def LDRH2 : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
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"ldrh $dst, [$addr]",
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[(set IntRegs:$dst, (extloadi16 IntRegs:$addr))]>;
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def LDRSH : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
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"ldrsh $dst, [$addr]",
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[(set IntRegs:$dst, (sextloadi16 IntRegs:$addr))]>;
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