forked from OSchip/llvm-project
Revert "[sve][acle] Add reinterpret intrinsics for brain float."
This reverts commit a15722c5ce
.
The commmit has to be reverted because I accidentally submit
https://reviews.llvm.org/D82501 without the C tests that were added in
an early version of the patch.
This commit is contained in:
parent
467ba4c92f
commit
ff5ccf258e
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@ -248,13 +248,13 @@ private:
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const char *Type;
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const char *Type;
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const char *BuiltinType;
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const char *BuiltinType;
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};
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};
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SmallVector<ReinterpretTypeInfo, 12> Reinterprets = {
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SmallVector<ReinterpretTypeInfo, 11> Reinterprets = {
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{"s8", "svint8_t", "q16Sc"}, {"s16", "svint16_t", "q8Ss"},
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{"s8", "svint8_t", "q16Sc"}, {"s16", "svint16_t", "q8Ss"},
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{"s32", "svint32_t", "q4Si"}, {"s64", "svint64_t", "q2SWi"},
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{"s32", "svint32_t", "q4Si"}, {"s64", "svint64_t", "q2SWi"},
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{"u8", "svuint8_t", "q16Uc"}, {"u16", "svuint16_t", "q8Us"},
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{"u8", "svuint8_t", "q16Uc"}, {"u16", "svuint16_t", "q8Us"},
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{"u32", "svuint32_t", "q4Ui"}, {"u64", "svuint64_t", "q2UWi"},
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{"u32", "svuint32_t", "q4Ui"}, {"u64", "svuint64_t", "q2UWi"},
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{"f16", "svfloat16_t", "q8h"}, {"bf16", "svbfloat16_t", "q8y"},
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{"f16", "svfloat16_t", "q8h"}, {"f32", "svfloat32_t", "q4f"},
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{"f32", "svfloat32_t", "q4f"}, {"f64", "svfloat64_t", "q2d"}};
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{"f64", "svfloat64_t", "q2d"}};
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RecordKeeper &Records;
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RecordKeeper &Records;
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llvm::StringMap<uint64_t> EltTypes;
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llvm::StringMap<uint64_t> EltTypes;
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@ -1208,10 +1208,6 @@ void SVEEmitter::createHeader(raw_ostream &OS) {
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for (auto ShortForm : { false, true } )
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for (auto ShortForm : { false, true } )
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for (const ReinterpretTypeInfo &From : Reinterprets)
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for (const ReinterpretTypeInfo &From : Reinterprets)
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for (const ReinterpretTypeInfo &To : Reinterprets) {
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for (const ReinterpretTypeInfo &To : Reinterprets) {
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const bool IsBFloat = StringRef(From.Suffix).equals("bf16") ||
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StringRef(To.Suffix).equals("bf16");
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if (IsBFloat)
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OS << "#if defined(__ARM_FEATURE_SVE_BF16)\n";
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if (ShortForm) {
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if (ShortForm) {
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OS << "__aio " << From.Type << " svreinterpret_" << From.Suffix;
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OS << "__aio " << From.Type << " svreinterpret_" << From.Suffix;
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OS << "(" << To.Type << " op) {\n";
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OS << "(" << To.Type << " op) {\n";
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@ -1222,8 +1218,6 @@ void SVEEmitter::createHeader(raw_ostream &OS) {
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OS << "#define svreinterpret_" << From.Suffix << "_" << To.Suffix
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OS << "#define svreinterpret_" << From.Suffix << "_" << To.Suffix
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<< "(...) __builtin_sve_reinterpret_" << From.Suffix << "_"
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<< "(...) __builtin_sve_reinterpret_" << From.Suffix << "_"
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<< To.Suffix << "(__VA_ARGS__)\n";
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<< To.Suffix << "(__VA_ARGS__)\n";
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if (IsBFloat)
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OS << "#endif /* #if defined(__ARM_FEATURE_SVE_BF16) */\n";
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}
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}
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SmallVector<std::unique_ptr<Intrinsic>, 128> Defs;
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SmallVector<std::unique_ptr<Intrinsic>, 128> Defs;
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@ -1466,6 +1466,7 @@ multiclass sve_prefetch<SDPatternOperator prefetch, ValueType PredTy, Instructio
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def : Pat<(nxv8f16 (bitconvert (nxv16i8 ZPR:$src))), (nxv8f16 ZPR:$src)>;
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def : Pat<(nxv8f16 (bitconvert (nxv16i8 ZPR:$src))), (nxv8f16 ZPR:$src)>;
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def : Pat<(nxv8f16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8f16 ZPR:$src)>;
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def : Pat<(nxv8f16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8f16 ZPR:$src)>;
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def : Pat<(nxv8bf16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
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def : Pat<(nxv8f16 (bitconvert (nxv4i32 ZPR:$src))), (nxv8f16 ZPR:$src)>;
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def : Pat<(nxv8f16 (bitconvert (nxv4i32 ZPR:$src))), (nxv8f16 ZPR:$src)>;
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def : Pat<(nxv8f16 (bitconvert (nxv2i64 ZPR:$src))), (nxv8f16 ZPR:$src)>;
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def : Pat<(nxv8f16 (bitconvert (nxv2i64 ZPR:$src))), (nxv8f16 ZPR:$src)>;
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def : Pat<(nxv8f16 (bitconvert (nxv4f32 ZPR:$src))), (nxv8f16 ZPR:$src)>;
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def : Pat<(nxv8f16 (bitconvert (nxv4f32 ZPR:$src))), (nxv8f16 ZPR:$src)>;
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@ -1486,24 +1487,6 @@ multiclass sve_prefetch<SDPatternOperator prefetch, ValueType PredTy, Instructio
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def : Pat<(nxv2f64 (bitconvert (nxv4f32 ZPR:$src))), (nxv2f64 ZPR:$src)>;
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def : Pat<(nxv2f64 (bitconvert (nxv4f32 ZPR:$src))), (nxv2f64 ZPR:$src)>;
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}
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}
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let Predicates = [IsLE, HasSVE, HasBF16] in {
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def : Pat<(nxv8bf16 (bitconvert (nxv16i8 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
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def : Pat<(nxv8bf16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
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def : Pat<(nxv8bf16 (bitconvert (nxv4i32 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
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def : Pat<(nxv8bf16 (bitconvert (nxv2i64 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
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def : Pat<(nxv8bf16 (bitconvert (nxv8f16 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
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def : Pat<(nxv8bf16 (bitconvert (nxv4f32 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
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def : Pat<(nxv8bf16 (bitconvert (nxv2f64 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
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def : Pat<(nxv16i8 (bitconvert (nxv8bf16 ZPR:$src))), (nxv16i8 ZPR:$src)>;
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def : Pat<(nxv8i16 (bitconvert (nxv8bf16 ZPR:$src))), (nxv8i16 ZPR:$src)>;
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def : Pat<(nxv4i32 (bitconvert (nxv8bf16 ZPR:$src))), (nxv4i32 ZPR:$src)>;
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def : Pat<(nxv2i64 (bitconvert (nxv8bf16 ZPR:$src))), (nxv2i64 ZPR:$src)>;
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def : Pat<(nxv8f16 (bitconvert (nxv8bf16 ZPR:$src))), (nxv8f16 ZPR:$src)>;
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def : Pat<(nxv4f32 (bitconvert (nxv8bf16 ZPR:$src))), (nxv4f32 ZPR:$src)>;
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def : Pat<(nxv2f64 (bitconvert (nxv8bf16 ZPR:$src))), (nxv2f64 ZPR:$src)>;
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}
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def : Pat<(nxv16i1 (reinterpret_cast (nxv16i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>;
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def : Pat<(nxv16i1 (reinterpret_cast (nxv16i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>;
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def : Pat<(nxv16i1 (reinterpret_cast (nxv8i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>;
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def : Pat<(nxv16i1 (reinterpret_cast (nxv8i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>;
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def : Pat<(nxv16i1 (reinterpret_cast (nxv4i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>;
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def : Pat<(nxv16i1 (reinterpret_cast (nxv4i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>;
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@ -340,118 +340,3 @@ define <vscale x 2 x double> @bitcast_float_to_double(<vscale x 4 x float> %v) {
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%bc = bitcast <vscale x 4 x float> %v to <vscale x 2 x double>
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%bc = bitcast <vscale x 4 x float> %v to <vscale x 2 x double>
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ret <vscale x 2 x double> %bc
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ret <vscale x 2 x double> %bc
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}
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}
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define <vscale x 16 x i8> @bitcast_bfloat_to_i8(<vscale x 8 x bfloat> %v) #0 {
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; CHECK-LABEL: bitcast_bfloat_to_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%bc = bitcast <vscale x 8 x bfloat> %v to <vscale x 16 x i8>
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ret <vscale x 16 x i8> %bc
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}
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define <vscale x 8 x i16> @bitcast_bfloat_to_i16(<vscale x 8 x bfloat> %v) #0 {
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; CHECK-LABEL: bitcast_bfloat_to_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%bc = bitcast <vscale x 8 x bfloat> %v to <vscale x 8 x i16>
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ret <vscale x 8 x i16> %bc
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}
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define <vscale x 4 x i32> @bitcast_bfloat_to_i32(<vscale x 8 x bfloat> %v) #0 {
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; CHECK-LABEL: bitcast_bfloat_to_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%bc = bitcast <vscale x 8 x bfloat> %v to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %bc
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}
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define <vscale x 2 x i64> @bitcast_bfloat_to_i64(<vscale x 8 x bfloat> %v) #0 {
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; CHECK-LABEL: bitcast_bfloat_to_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%bc = bitcast <vscale x 8 x bfloat> %v to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %bc
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}
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define <vscale x 8 x half> @bitcast_bfloat_to_half(<vscale x 8 x bfloat> %v) #0 {
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; CHECK-LABEL: bitcast_bfloat_to_half:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%bc = bitcast <vscale x 8 x bfloat> %v to <vscale x 8 x half>
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ret <vscale x 8 x half> %bc
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}
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define <vscale x 4 x float> @bitcast_bfloat_to_float(<vscale x 8 x bfloat> %v) #0 {
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; CHECK-LABEL: bitcast_bfloat_to_float:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%bc = bitcast <vscale x 8 x bfloat> %v to <vscale x 4 x float>
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ret <vscale x 4 x float> %bc
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}
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define <vscale x 2 x double> @bitcast_bfloat_to_double(<vscale x 8 x bfloat> %v) #0 {
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; CHECK-LABEL: bitcast_bfloat_to_double:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%bc = bitcast <vscale x 8 x bfloat> %v to <vscale x 2 x double>
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ret <vscale x 2 x double> %bc
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}
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define <vscale x 8 x bfloat> @bitcast_i8_to_bfloat(<vscale x 16 x i8> %v) #0 {
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; CHECK-LABEL: bitcast_i8_to_bfloat:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%bc = bitcast <vscale x 16 x i8> %v to <vscale x 8 x bfloat>
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ret <vscale x 8 x bfloat> %bc
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}
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define <vscale x 8 x bfloat> @bitcast_i16_to_bfloat(<vscale x 8 x i16> %v) #0 {
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; CHECK-LABEL: bitcast_i16_to_bfloat:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%bc = bitcast <vscale x 8 x i16> %v to <vscale x 8 x bfloat>
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ret <vscale x 8 x bfloat> %bc
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}
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define <vscale x 8 x bfloat> @bitcast_i32_to_bfloat(<vscale x 4 x i32> %v) #0 {
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; CHECK-LABEL: bitcast_i32_to_bfloat:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%bc = bitcast <vscale x 4 x i32> %v to <vscale x 8 x bfloat>
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ret <vscale x 8 x bfloat> %bc
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}
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define <vscale x 8 x bfloat> @bitcast_i64_to_bfloat(<vscale x 2 x i64> %v) #0 {
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; CHECK-LABEL: bitcast_i64_to_bfloat:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%bc = bitcast <vscale x 2 x i64> %v to <vscale x 8 x bfloat>
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ret <vscale x 8 x bfloat> %bc
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}
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define <vscale x 8 x bfloat> @bitcast_half_to_bfloat(<vscale x 8 x half> %v) #0 {
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; CHECK-LABEL: bitcast_half_to_bfloat:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%bc = bitcast <vscale x 8 x half> %v to <vscale x 8 x bfloat>
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ret <vscale x 8 x bfloat> %bc
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}
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define <vscale x 8 x bfloat> @bitcast_float_to_bfloat(<vscale x 4 x float> %v) #0 {
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; CHECK-LABEL: bitcast_float_to_bfloat:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%bc = bitcast <vscale x 4 x float> %v to <vscale x 8 x bfloat>
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ret <vscale x 8 x bfloat> %bc
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}
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define <vscale x 8 x bfloat> @bitcast_double_to_bfloat(<vscale x 2 x double> %v) #0 {
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; CHECK-LABEL: bitcast_double_to_bfloat:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%bc = bitcast <vscale x 2 x double> %v to <vscale x 8 x bfloat>
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ret <vscale x 8 x bfloat> %bc
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}
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; +bf16 is required for the bfloat version.
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attributes #0 = { "target-features"="+sve,+bf16" }
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