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[DeLICM] Fix wrong assumed access execution order. 

ForwardOpTree may already transform a scalar access to an array
accesses. The access remains implicit (isOriginalScalarKind(), meaning
that the access is always executed at the begin/end of a statement), but
targets an array (isLatestArrayKind(), which is unrelated to whether the
execution is implicit/explicit).

Fix by properly using isOriginalXXX() to determine execution order.

This fixes the buildbots on MultiSource/Benchmarks/DOE-ProxyApps-C/miniGMG.

llvm-svn: 316995
This commit is contained in:
Michael Kruse 2017-10-31 12:50:25 +00:00
parent b6915fbfa2
commit ff426d974d
4 changed files with 136 additions and 1 deletions
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2
polly/lib/Transform/ZoneAlgo.cpp
View File

@ -321,7 +321,7 @@ void ZoneAlgorithm::collectIncompatibleElts(ScopStmt *Stmt,
// This assumes that the MemoryKind::Array MemoryAccesses are iterated in
// order.
for (auto *MA : *Stmt) {
if (!MA->isLatestArrayKind())
if (!MA->isOriginalArrayKind())
continue;
isl::map AccRelMap = getAccessRelationFor(MA);

41
polly/test/DeLICM/confused_order.ll Normal file
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@ -0,0 +1,41 @@
; RUN: opt %loadPolly -polly-import-jscop -polly-import-jscop-postfix=transformed -polly-delicm -analyze < %s | FileCheck %s
; RUN: opt %loadPolly -polly-import-jscop -polly-import-jscop-postfix=transformed -polly-delicm -disable-output -pass-remarks-missed=polly-delicm < %s 2>&1 | FileCheck %s -check-prefix=REMARKS
;
; ForwardOptree changes the SCoP and may already map some accesses.
; DeLICM must be prepared to encounter implicit reads
; (isOriginalScalarKind()) that occur at the beginning of the SCoP
; to an array (isLatestArrayKind()). Otherwise it may confuse the
; MemoryAccess execution order.
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
define void @confused_order(double* nocapture %C, i32 %rows, i32 %cols) {
entry:
%0 = sext i32 %cols to i64
%1 = sext i32 %rows to i64
%cmp108 = icmp slt i64 0, %0
br i1 undef, label %for.body7.lr.ph, label %for.end103
for.body7.lr.ph:
br label %for.end103
for.end103:
%a_dot_b_domain.0.lcssa = phi double [ 0.000000e+00, %entry ], [ undef, %for.body7.lr.ph ]
%arrayidx107 = getelementptr inbounds double, double* %C, i64 0
store double %a_dot_b_domain.0.lcssa, double* %arrayidx107
%cmp109 = icmp slt i64 0, %1
%or.cond = and i1 %cmp108, %cmp109
br i1 %or.cond, label %if.then110, label %for.inc116
if.then110:
%arrayidx114 = getelementptr inbounds double, double* %C, i64 0
store double %a_dot_b_domain.0.lcssa, double* %arrayidx114
br label %for.inc116
for.inc116:
ret void
}
; REMARKS-NOT: load after store of same element in same statement
; CHECK: No modification has been made

47
polly/test/DeLICM/confused_order___%for.end103---%for.inc116.jscop Normal file
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@ -0,0 +1,47 @@
{
"arrays" : [
{
"name" : "MemRef_C",
"sizes" : [ "*" ],
"type" : "double"
}
],
"context" : "[cols, rows] -> { : -2147483648 <= cols <= 2147483647 and -2147483648 <= rows <= 2147483647 }",
"name" : "%for.end103---%for.inc116",
"statements" : [
{
"accesses" : [
{
"kind" : "read",
"relation" : "[cols, rows] -> { Stmt_for_end103[] -> MemRef_a_dot_b_domain_0_lcssa__phi[] }"
},
{
"kind" : "write",
"relation" : "[cols, rows] -> { Stmt_for_end103[] -> MemRef_C[0] }"
},
{
"kind" : "write",
"relation" : "[cols, rows] -> { Stmt_for_end103[] -> MemRef_a_dot_b_domain_0_lcssa[] }"
}
],
"domain" : "[cols, rows] -> { Stmt_for_end103[] }",
"name" : "Stmt_for_end103",
"schedule" : "[cols, rows] -> { Stmt_for_end103[] -> [0] }"
},
{
"accesses" : [
{
"kind" : "write",
"relation" : "[cols, rows] -> { Stmt_if_then110[] -> MemRef_C[0] }"
},
{
"kind" : "read",
"relation" : "[cols, rows] -> { Stmt_if_then110[] -> MemRef_a_dot_b_domain_0_lcssa[] }"
}
],
"domain" : "[cols, rows] -> { Stmt_if_then110[] : cols > 0 and rows > 0 }",
"name" : "Stmt_if_then110",
"schedule" : "[cols, rows] -> { Stmt_if_then110[] -> [1] }"
}
]
}

47
polly/test/DeLICM/confused_order___%for.end103---%for.inc116.jscop.transformed Normal file
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@ -0,0 +1,47 @@
{
"arrays" : [
{
"name" : "MemRef_C",
"sizes" : [ "*" ],
"type" : "double"
}
],
"context" : "[cols, rows] -> { : -2147483648 <= cols <= 2147483647 and -2147483648 <= rows <= 2147483647 }",
"name" : "%for.end103---%for.inc116",
"statements" : [
{
"accesses" : [
{
"kind" : "read",
"relation" : "[cols, rows] -> { Stmt_for_end103[] -> MemRef_a_dot_b_domain_0_lcssa__phi[] }"
},
{
"kind" : "write",
"relation" : "[cols, rows] -> { Stmt_for_end103[] -> MemRef_C[0] }"
},
{
"kind" : "write",
"relation" : "[cols, rows] -> { Stmt_for_end103[] -> MemRef_a_dot_b_domain_0_lcssa[] }"
}
],
"domain" : "[cols, rows] -> { Stmt_for_end103[] }",
"name" : "Stmt_for_end103",
"schedule" : "[cols, rows] -> { Stmt_for_end103[] -> [0] }"
},
{
"accesses" : [
{
"kind" : "write",
"relation" : "[cols, rows] -> { Stmt_if_then110[] -> MemRef_C[0] }"
},
{
"kind" : "read",
"relation" : "[cols, rows] -> { Stmt_if_then110[] -> MemRef_C[0] }"
}
],
"domain" : "[cols, rows] -> { Stmt_if_then110[] : cols > 0 and rows > 0 }",
"name" : "Stmt_if_then110",
"schedule" : "[cols, rows] -> { Stmt_if_then110[] -> [1] }"
}
]
}