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[AArch64][AsmParser] Arch directives should set implied features. 

When assembling for example an SVE instruction with the `.arch +sve2` directive,
+sve should be implied by setting +sve2, similar to what would happen if
one would pass the mattr=+sve2 flag on the command-line.

The AsmParser doesn't set the implied features, meaning that the SVE
instruction does not assemble. This patch fixes that.

Note that the same does not hold when disabling a feature. For example,
+nosve2 does not imply +nosve.

Reviewed By: c-rhodes

Differential Revision: https://reviews.llvm.org/D120259
This commit is contained in:
Sander de Smalen 2022-02-24 08:46:15 +00:00
parent dbc4d281bd
commit ff3f3a54e2
5 changed files with 55 additions and 19 deletions
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35
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
View File

@ -6214,12 +6214,11 @@ bool AArch64AsmParser::parseDirectiveArch(SMLoc L) {
if (Extension.Features.none()) if (Extension.Features.none())
report_fatal_error("unsupported architectural extension: " + Name); report_fatal_error("unsupported architectural extension: " + Name);
FeatureBitset ToggleFeatures = EnableFeature FeatureBitset ToggleFeatures =
? (~Features & Extension.Features) EnableFeature
: ( Features & Extension.Features); ? STI.SetFeatureBitsTransitively(~Features & Extension.Features)
FeatureBitset Features = : STI.ToggleFeature(Features & Extension.Features);
ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures)); setAvailableFeatures(ComputeAvailableFeatures(ToggleFeatures));
setAvailableFeatures(Features);
break; break;
} }
} }
@ -6252,12 +6251,11 @@ bool AArch64AsmParser::parseDirectiveArchExtension(SMLoc L) {
if (Extension.Features.none()) if (Extension.Features.none())
return Error(ExtLoc, "unsupported architectural extension: " + Name); return Error(ExtLoc, "unsupported architectural extension: " + Name);
FeatureBitset ToggleFeatures = EnableFeature FeatureBitset ToggleFeatures =
? (~Features & Extension.Features) EnableFeature
: (Features & Extension.Features); ? STI.SetFeatureBitsTransitively(~Features & Extension.Features)
FeatureBitset Features = : STI.ToggleFeature(Features & Extension.Features);
ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures)); setAvailableFeatures(ComputeAvailableFeatures(ToggleFeatures));
setAvailableFeatures(Features);
return false; return false;
} }
@ -6297,7 +6295,6 @@ bool AArch64AsmParser::parseDirectiveCPU(SMLoc L) {
ExpandCryptoAEK(llvm::AArch64::getCPUArchKind(CPU), RequestedExtensions); ExpandCryptoAEK(llvm::AArch64::getCPUArchKind(CPU), RequestedExtensions);
FeatureBitset Features = STI.getFeatureBits();
for (auto Name : RequestedExtensions) { for (auto Name : RequestedExtensions) {
// Advance source location past '+'. // Advance source location past '+'.
CurLoc = incrementLoc(CurLoc, 1); CurLoc = incrementLoc(CurLoc, 1);
@ -6317,12 +6314,12 @@ bool AArch64AsmParser::parseDirectiveCPU(SMLoc L) {
if (Extension.Features.none()) if (Extension.Features.none())
report_fatal_error("unsupported architectural extension: " + Name); report_fatal_error("unsupported architectural extension: " + Name);
FeatureBitset ToggleFeatures = EnableFeature FeatureBitset Features = STI.getFeatureBits();
? (~Features & Extension.Features) FeatureBitset ToggleFeatures =
: ( Features & Extension.Features); EnableFeature
FeatureBitset Features = ? STI.SetFeatureBitsTransitively(~Features & Extension.Features)
ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures)); : STI.ToggleFeature(Features & Extension.Features);
setAvailableFeatures(Features); setAvailableFeatures(ComputeAvailableFeatures(ToggleFeatures));
FoundExtension = true; FoundExtension = true;
break; break;

6
llvm/test/MC/AArch64/SVE/directive-arch.s
View File

@ -4,3 +4,9 @@
ptrue p0.b, pow2 ptrue p0.b, pow2
// CHECK: ptrue p0.b, pow2 // CHECK: ptrue p0.b, pow2
// Test that the implied +sve feature is also set from +sve2.
.arch armv8-a+sve2
ptrue p0.b, pow2
// CHECK: ptrue p0.b, pow2

12
llvm/test/MC/AArch64/SVE/directive-arch_extension.s
View File

@ -4,3 +4,15 @@
ptrue p0.b, pow2 ptrue p0.b, pow2
// CHECK: ptrue p0.b, pow2 // CHECK: ptrue p0.b, pow2
// Test that the implied +sve feature is also set from +sve2.
.arch_extension nosve
.arch_extension sve2
ptrue p0.b, pow2
// CHECK: ptrue p0.b, pow2
// Check that setting +nosve2 does not imply +nosve
.arch_extension nosve2
ptrue p0.b, pow2
// CHECK: ptrue p0.b, pow2

6
llvm/test/MC/AArch64/SVE/directive-cpu-negative.s Normal file
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@ -0,0 +1,6 @@
// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
.cpu generic+sve+nosve
ptrue p0.b, pow2
// CHECK: error: instruction requires: sve or sme
// CHECK-NEXT: ptrue p0.b, pow2

15
llvm/test/MC/AArch64/SVE/directive-cpu.s Normal file
View File

@ -0,0 +1,15 @@
// RUN: llvm-mc -triple=aarch64 < %s | FileCheck %s
.cpu generic+sve
ptrue p0.b, pow2
// CHECK: ptrue p0.b, pow2
// Test that the implied +sve feature is also set from +sve2.
.cpu generic+sve2
ptrue p0.b, pow2
// CHECK: ptrue p0.b, pow2
// Check that setting +nosve2 does not imply +nosve
.cpu generic+sve2+nosve2
ptrue p0.b, pow2
// CHECK: ptrue p0.b, pow2