forked from OSchip/llvm-project
[DAGCombiner] unify type checks and add asserts; NFCI
We had a mix of type checks and usage that wasn't very clear. llvm-svn: 299013
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@ -3178,68 +3178,74 @@ SDValue DAGCombiner::foldAndOfSetCCs(SDValue N0, SDValue N1, const SDLoc &DL) {
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!isSetCCEquivalent(N1, RL, RR, N1CC))
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return SDValue();
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assert(N0.getValueType() == N1.getValueType() &&
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"Unexpected operand types for 'and' op");
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assert(LL.getValueType() == LR.getValueType() &&
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RL.getValueType() == RR.getValueType() &&
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"Unexpected operand types for setcc");
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// If we're here post-legalization or the 'and' is not i1, the 'and' type must
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// match a setcc result type. Also, all folds require new operations on the
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// left and right operands, so those types must match.
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EVT VT = N0.getValueType();
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EVT OpVT = LL.getValueType();
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if (LegalOperations || VT != MVT::i1)
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if (VT != getSetCCResultType(OpVT))
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return SDValue();
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if (OpVT != RL.getValueType())
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return SDValue();
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ISD::CondCode CC0 = cast<CondCodeSDNode>(N0CC)->get();
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ISD::CondCode CC1 = cast<CondCodeSDNode>(N1CC)->get();
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EVT VT = N1.getValueType();
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assert(VT == N0.getValueType() && "Unexpected operand types for 'and'");
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EVT LLVT = LL.getValueType();
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EVT LRVT = LR.getValueType();
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bool IsInteger = LLVT.isInteger();
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bool IsInteger = OpVT.isInteger();
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if (LR == RR && CC0 == CC1 && IsInteger) {
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EVT CCVT = getSetCCResultType(LRVT);
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if (VT == CCVT || (!LegalOperations && VT == MVT::i1)) {
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// (and (seteq X, 0), (seteq Y, 0)) --> (seteq (or X, Y), 0)
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if (isNullConstant(LR) && CC1 == ISD::SETEQ) {
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SDValue Or = DAG.getNode(ISD::OR, SDLoc(N0), LRVT, LL, RL);
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AddToWorklist(Or.getNode());
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return DAG.getSetCC(DL, VT, Or, LR, CC1);
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}
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// (and (seteq X, 0), (seteq Y, 0)) --> (seteq (or X, Y), 0)
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if (isNullConstant(LR) && CC1 == ISD::SETEQ) {
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SDValue Or = DAG.getNode(ISD::OR, SDLoc(N0), OpVT, LL, RL);
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AddToWorklist(Or.getNode());
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return DAG.getSetCC(DL, VT, Or, LR, CC1);
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}
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// (and (seteq X, -1), (seteq Y, -1)) --> (seteq (and X, Y), -1)
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if (isAllOnesConstant(LR) && CC1 == ISD::SETEQ) {
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SDValue And = DAG.getNode(ISD::AND, SDLoc(N0), LRVT, LL, RL);
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AddToWorklist(And.getNode());
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return DAG.getSetCC(DL, VT, And, LR, CC1);
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}
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// (and (seteq X, -1), (seteq Y, -1)) --> (seteq (and X, Y), -1)
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if (isAllOnesConstant(LR) && CC1 == ISD::SETEQ) {
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SDValue And = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, LL, RL);
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AddToWorklist(And.getNode());
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return DAG.getSetCC(DL, VT, And, LR, CC1);
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}
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// (and (setgt X, -1), (setgt Y, -1)) --> (setgt (or X, Y), -1)
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if (isAllOnesConstant(LR) && CC1 == ISD::SETGT) {
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SDValue Or = DAG.getNode(ISD::OR, SDLoc(N0), LRVT, LL, RL);
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AddToWorklist(Or.getNode());
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return DAG.getSetCC(DL, VT, Or, LR, CC1);
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}
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// (and (setgt X, -1), (setgt Y, -1)) --> (setgt (or X, Y), -1)
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if (isAllOnesConstant(LR) && CC1 == ISD::SETGT) {
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SDValue Or = DAG.getNode(ISD::OR, SDLoc(N0), OpVT, LL, RL);
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AddToWorklist(Or.getNode());
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return DAG.getSetCC(DL, VT, Or, LR, CC1);
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}
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}
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EVT CCVT = getSetCCResultType(LLVT);
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if (VT == CCVT || (!LegalOperations && VT == MVT::i1)) {
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// (and (setne X, 0), (setne X, -1)) --> (setuge (add X, 1), 2)
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if (LL == RL && CC0 == CC1 && IsInteger && CC0 == ISD::SETNE &&
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((isNullConstant(LR) && isAllOnesConstant(RR)) ||
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(isAllOnesConstant(LR) && isNullConstant(RR)))) {
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SDValue One = DAG.getConstant(1, DL, LLVT);
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SDValue Two = DAG.getConstant(2, DL, LLVT);
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SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0), LLVT, LL, One);
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AddToWorklist(Add.getNode());
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return DAG.getSetCC(DL, VT, Add, Two, ISD::SETUGE);
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}
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// (and (setne X, 0), (setne X, -1)) --> (setuge (add X, 1), 2)
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if (LL == RL && CC0 == CC1 && IsInteger && CC0 == ISD::SETNE &&
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((isNullConstant(LR) && isAllOnesConstant(RR)) ||
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(isAllOnesConstant(LR) && isNullConstant(RR)))) {
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SDValue One = DAG.getConstant(1, DL, OpVT);
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SDValue Two = DAG.getConstant(2, DL, OpVT);
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SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0), OpVT, LL, One);
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AddToWorklist(Add.getNode());
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return DAG.getSetCC(DL, VT, Add, Two, ISD::SETUGE);
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}
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// Canonicalize equivalent operands to LL == RL.
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if (LL == RR && LR == RL) {
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CC1 = ISD::getSetCCSwappedOperands(CC1);
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std::swap(RL, RR);
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}
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// Canonicalize equivalent operands to LL == RL.
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if (LL == RR && LR == RL) {
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CC1 = ISD::getSetCCSwappedOperands(CC1);
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std::swap(RL, RR);
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}
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// (and (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC)
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if (LL == RL && LR == RR) {
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ISD::CondCode NewCC = ISD::getSetCCAndOperation(CC0, CC1, IsInteger);
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if (NewCC != ISD::SETCC_INVALID &&
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(!LegalOperations ||
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(TLI.isCondCodeLegal(NewCC, LL.getSimpleValueType()) &&
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TLI.isOperationLegal(ISD::SETCC, LLVT))))
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return DAG.getSetCC(DL, VT, LL, LR, NewCC);
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}
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// (and (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC)
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if (LL == RL && LR == RR) {
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ISD::CondCode NewCC = ISD::getSetCCAndOperation(CC0, CC1, IsInteger);
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if (NewCC != ISD::SETCC_INVALID &&
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(!LegalOperations ||
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(TLI.isCondCodeLegal(NewCC, LL.getSimpleValueType()) &&
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TLI.isOperationLegal(ISD::SETCC, OpVT))))
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return DAG.getSetCC(DL, VT, LL, LR, NewCC);
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}
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return SDValue();
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