forked from OSchip/llvm-project
[X86][XOP] createVariablePermute - use VPPERM for v16i16 variable permutes
llvm-svn: 327218
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parent
d9dc114e2f
commit
ff1248f82f
llvm
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@ -8010,6 +8010,14 @@ SDValue createVariablePermute(MVT VT, SDValue SrcVec, SDValue IndicesVec,
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case MVT::v16i16:
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if (Subtarget.hasVLX() && Subtarget.hasBWI())
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Opcode = X86ISD::VPERMV;
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else if (Subtarget.hasXOP()) {
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// Scale to v32i8 and perform as v32i8.
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IndicesVec = ScaleIndices(IndicesVec, 2);
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return DAG.getBitcast(
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VT, createVariablePermute(
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MVT::v32i8, DAG.getBitcast(MVT::v32i8, SrcVec),
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DAG.getBitcast(MVT::v32i8, IndicesVec), DL, DAG, Subtarget));
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}
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break;
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case MVT::v8f32:
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case MVT::v8i32:
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@ -239,65 +239,15 @@ define <8 x i32> @var_shuffle_v8i32(<8 x i32> %v, <8 x i32> %indices) nounwind {
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define <16 x i16> @var_shuffle_v16i16(<16 x i16> %v, <16 x i16> %indices) nounwind {
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; XOP-LABEL: var_shuffle_v16i16:
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; XOP: # %bb.0:
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; XOP-NEXT: pushq %rbp
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; XOP-NEXT: movq %rsp, %rbp
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; XOP-NEXT: andq $-32, %rsp
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; XOP-NEXT: subq $64, %rsp
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; XOP-NEXT: vextractf128 $1, %ymm1, %xmm2
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; XOP-NEXT: vmovd %xmm2, %eax
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; XOP-NEXT: vmovaps %ymm0, (%rsp)
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; XOP-NEXT: andl $15, %eax
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; XOP-NEXT: movzwl (%rsp,%rax,2), %eax
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; XOP-NEXT: vmovd %eax, %xmm0
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; XOP-NEXT: vpextrw $1, %xmm2, %eax
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; XOP-NEXT: andl $15, %eax
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; XOP-NEXT: vpinsrw $1, (%rsp,%rax,2), %xmm0, %xmm0
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; XOP-NEXT: vpextrw $2, %xmm2, %eax
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; XOP-NEXT: andl $15, %eax
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; XOP-NEXT: vpinsrw $2, (%rsp,%rax,2), %xmm0, %xmm0
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; XOP-NEXT: vpextrw $3, %xmm2, %eax
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; XOP-NEXT: andl $15, %eax
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; XOP-NEXT: vpinsrw $3, (%rsp,%rax,2), %xmm0, %xmm0
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; XOP-NEXT: vpextrw $4, %xmm2, %eax
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; XOP-NEXT: andl $15, %eax
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; XOP-NEXT: vpinsrw $4, (%rsp,%rax,2), %xmm0, %xmm0
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; XOP-NEXT: vpextrw $5, %xmm2, %eax
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; XOP-NEXT: andl $15, %eax
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; XOP-NEXT: vpinsrw $5, (%rsp,%rax,2), %xmm0, %xmm0
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; XOP-NEXT: vpextrw $6, %xmm2, %eax
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; XOP-NEXT: andl $15, %eax
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; XOP-NEXT: vpinsrw $6, (%rsp,%rax,2), %xmm0, %xmm0
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; XOP-NEXT: vpextrw $7, %xmm2, %eax
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; XOP-NEXT: andl $15, %eax
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; XOP-NEXT: vpinsrw $7, (%rsp,%rax,2), %xmm0, %xmm0
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; XOP-NEXT: vmovd %xmm1, %eax
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; XOP-NEXT: andl $15, %eax
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; XOP-NEXT: movzwl (%rsp,%rax,2), %eax
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; XOP-NEXT: vmovd %eax, %xmm2
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; XOP-NEXT: vpextrw $1, %xmm1, %eax
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; XOP-NEXT: andl $15, %eax
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; XOP-NEXT: vpinsrw $1, (%rsp,%rax,2), %xmm2, %xmm2
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; XOP-NEXT: vpextrw $2, %xmm1, %eax
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; XOP-NEXT: andl $15, %eax
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; XOP-NEXT: vpinsrw $2, (%rsp,%rax,2), %xmm2, %xmm2
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; XOP-NEXT: vpextrw $3, %xmm1, %eax
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; XOP-NEXT: andl $15, %eax
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; XOP-NEXT: vpinsrw $3, (%rsp,%rax,2), %xmm2, %xmm2
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; XOP-NEXT: vpextrw $4, %xmm1, %eax
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; XOP-NEXT: andl $15, %eax
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; XOP-NEXT: vpinsrw $4, (%rsp,%rax,2), %xmm2, %xmm2
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; XOP-NEXT: vpextrw $5, %xmm1, %eax
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; XOP-NEXT: andl $15, %eax
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; XOP-NEXT: vpinsrw $5, (%rsp,%rax,2), %xmm2, %xmm2
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; XOP-NEXT: vpextrw $6, %xmm1, %eax
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; XOP-NEXT: andl $15, %eax
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; XOP-NEXT: vpinsrw $6, (%rsp,%rax,2), %xmm2, %xmm2
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; XOP-NEXT: vpextrw $7, %xmm1, %eax
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; XOP-NEXT: andl $15, %eax
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; XOP-NEXT: vpinsrw $7, (%rsp,%rax,2), %xmm2, %xmm1
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; XOP-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; XOP-NEXT: movq %rbp, %rsp
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; XOP-NEXT: popq %rbp
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; XOP-NEXT: vmovdqa {{.*#+}} xmm2 = [256,256,256,256,256,256,256,256]
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; XOP-NEXT: vmovdqa {{.*#+}} xmm3 = [514,514,514,514,514,514,514,514]
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; XOP-NEXT: vpmacsww %xmm2, %xmm3, %xmm1, %xmm4
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; XOP-NEXT: vextractf128 $1, %ymm1, %xmm1
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; XOP-NEXT: vpmacsww %xmm2, %xmm3, %xmm1, %xmm1
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; XOP-NEXT: vextractf128 $1, %ymm0, %xmm2
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; XOP-NEXT: vpperm %xmm1, %xmm2, %xmm0, %xmm1
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; XOP-NEXT: vpperm %xmm4, %xmm2, %xmm0, %xmm0
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; XOP-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; XOP-NEXT: retq
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;
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; AVX1-LABEL: var_shuffle_v16i16:
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@ -1858,59 +1808,14 @@ entry:
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define <16 x i16> @var_shuffle_v16i16_from_v8i16(<8 x i16> %v, <16 x i16> %indices) nounwind {
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; XOP-LABEL: var_shuffle_v16i16_from_v8i16:
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; XOP: # %bb.0:
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; XOP-NEXT: vextractf128 $1, %ymm1, %xmm2
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; XOP-NEXT: vmovd %xmm2, %eax
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; XOP-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
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; XOP-NEXT: andl $7, %eax
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; XOP-NEXT: movzwl -24(%rsp,%rax,2), %eax
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; XOP-NEXT: vmovd %eax, %xmm0
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; XOP-NEXT: vpextrw $1, %xmm2, %eax
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; XOP-NEXT: andl $7, %eax
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; XOP-NEXT: vpinsrw $1, -24(%rsp,%rax,2), %xmm0, %xmm0
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; XOP-NEXT: vpextrw $2, %xmm2, %eax
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; XOP-NEXT: andl $7, %eax
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; XOP-NEXT: vpinsrw $2, -24(%rsp,%rax,2), %xmm0, %xmm0
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; XOP-NEXT: vpextrw $3, %xmm2, %eax
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; XOP-NEXT: andl $7, %eax
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; XOP-NEXT: vpinsrw $3, -24(%rsp,%rax,2), %xmm0, %xmm0
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; XOP-NEXT: vpextrw $4, %xmm2, %eax
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; XOP-NEXT: andl $7, %eax
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; XOP-NEXT: vpinsrw $4, -24(%rsp,%rax,2), %xmm0, %xmm0
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; XOP-NEXT: vpextrw $5, %xmm2, %eax
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; XOP-NEXT: andl $7, %eax
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; XOP-NEXT: vpinsrw $5, -24(%rsp,%rax,2), %xmm0, %xmm0
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; XOP-NEXT: vpextrw $6, %xmm2, %eax
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; XOP-NEXT: andl $7, %eax
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; XOP-NEXT: vpinsrw $6, -24(%rsp,%rax,2), %xmm0, %xmm0
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; XOP-NEXT: vpextrw $7, %xmm2, %eax
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; XOP-NEXT: andl $7, %eax
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; XOP-NEXT: vpinsrw $7, -24(%rsp,%rax,2), %xmm0, %xmm0
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; XOP-NEXT: vmovd %xmm1, %eax
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; XOP-NEXT: andl $7, %eax
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; XOP-NEXT: movzwl -24(%rsp,%rax,2), %eax
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; XOP-NEXT: vmovd %eax, %xmm2
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; XOP-NEXT: vpextrw $1, %xmm1, %eax
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; XOP-NEXT: andl $7, %eax
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; XOP-NEXT: vpinsrw $1, -24(%rsp,%rax,2), %xmm2, %xmm2
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; XOP-NEXT: vpextrw $2, %xmm1, %eax
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; XOP-NEXT: andl $7, %eax
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; XOP-NEXT: vpinsrw $2, -24(%rsp,%rax,2), %xmm2, %xmm2
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; XOP-NEXT: vpextrw $3, %xmm1, %eax
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; XOP-NEXT: andl $7, %eax
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; XOP-NEXT: vpinsrw $3, -24(%rsp,%rax,2), %xmm2, %xmm2
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; XOP-NEXT: vpextrw $4, %xmm1, %eax
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; XOP-NEXT: andl $7, %eax
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; XOP-NEXT: vpinsrw $4, -24(%rsp,%rax,2), %xmm2, %xmm2
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; XOP-NEXT: vpextrw $5, %xmm1, %eax
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; XOP-NEXT: andl $7, %eax
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; XOP-NEXT: vpinsrw $5, -24(%rsp,%rax,2), %xmm2, %xmm2
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; XOP-NEXT: vpextrw $6, %xmm1, %eax
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; XOP-NEXT: andl $7, %eax
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; XOP-NEXT: vpinsrw $6, -24(%rsp,%rax,2), %xmm2, %xmm2
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; XOP-NEXT: vpextrw $7, %xmm1, %eax
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; XOP-NEXT: andl $7, %eax
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; XOP-NEXT: vpinsrw $7, -24(%rsp,%rax,2), %xmm2, %xmm1
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; XOP-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; XOP-NEXT: vmovdqa {{.*#+}} xmm2 = [256,256,256,256,256,256,256,256]
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; XOP-NEXT: vmovdqa {{.*#+}} xmm3 = [514,514,514,514,514,514,514,514]
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; XOP-NEXT: vpmacsww %xmm2, %xmm3, %xmm1, %xmm4
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; XOP-NEXT: vextractf128 $1, %ymm1, %xmm1
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; XOP-NEXT: vpmacsww %xmm2, %xmm3, %xmm1, %xmm1
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; XOP-NEXT: vpperm %xmm1, %xmm0, %xmm0, %xmm1
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; XOP-NEXT: vpperm %xmm4, %xmm0, %xmm0, %xmm0
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; XOP-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; XOP-NEXT: retq
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;
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; AVX1-LABEL: var_shuffle_v16i16_from_v8i16:
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