forked from OSchip/llvm-project
[X86][SSE] Recognise splat rotations and expand back to shift ops.
Noticed while fixing PR37426, for splat rotations (rotation by an uniform value) its better to just expand back to shift ops than performing as a general non-uniform rotation. llvm-svn: 333661
This commit is contained in:
Simon Pilgrim
parent
c34395d889
commit
ff0623cd29
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@ -23133,6 +23133,8 @@ static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
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static SDValue IsSplatValue(MVT VT, SDValue V, const SDLoc &dl,
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SelectionDAG &DAG, const X86Subtarget &Subtarget,
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unsigned Opcode) {
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V = peekThroughEXTRACT_SUBVECTORs(V);
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// Check if this is a splat build_vector node.
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if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(V)) {
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SDValue SplatAmt = BV->getSplatValue();
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@ -23792,6 +23794,16 @@ static SDValue LowerRotate(SDValue Op, const X86Subtarget &Subtarget,
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}
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}
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// Rotate by splat - expand back to shifts.
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// TODO - legalizers should be able to handle this.
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if (IsSplatValue(VT, Amt, DL, DAG, Subtarget, Opcode)) {
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SDValue AmtR = DAG.getConstant(EltSizeInBits, DL, VT);
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AmtR = DAG.getNode(ISD::SUB, DL, VT, AmtR, Amt);
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SDValue SHL = DAG.getNode(ISD::SHL, DL, VT, R, Amt);
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SDValue SRL = DAG.getNode(ISD::SRL, DL, VT, R, AmtR);
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return DAG.getNode(ISD::OR, DL, VT, SHL, SRL);
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}
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// AVX2 - best to fallback to variable shifts.
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// TODO - legalizers should be able to handle this.
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if (Subtarget.hasAVX2()) {
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@ -831,55 +831,42 @@ define <2 x i64> @splatvar_rotate_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
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define <4 x i32> @splatvar_rotate_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
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; SSE2-LABEL: splatvar_rotate_v4i32:
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; SSE2: # %bb.0:
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; SSE2-NEXT: xorps %xmm2, %xmm2
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; SSE2-NEXT: xorps %xmm3, %xmm3
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; SSE2-NEXT: movss {{.*#+}} xmm3 = xmm1[0],xmm3[1,2,3]
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
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; SSE2-NEXT: pslld $23, %xmm1
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; SSE2-NEXT: paddd {{.*}}(%rip), %xmm1
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; SSE2-NEXT: cvttps2dq %xmm1, %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
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; SSE2-NEXT: pmuludq %xmm1, %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
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; SSE2-NEXT: pmuludq %xmm2, %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
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; SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
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; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; SSE2-NEXT: por %xmm3, %xmm0
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; SSE2-NEXT: movdqa %xmm0, %xmm4
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; SSE2-NEXT: pslld %xmm3, %xmm4
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; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [32,32,32,32]
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; SSE2-NEXT: psubd %xmm1, %xmm3
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; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm3[0],xmm2[1,2,3]
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; SSE2-NEXT: psrld %xmm2, %xmm0
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; SSE2-NEXT: por %xmm4, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: splatvar_rotate_v4i32:
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; SSE41: # %bb.0:
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; SSE41-NEXT: pmovzxdq {{.*#+}} xmm2 = xmm1[0],zero,xmm1[1],zero
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; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
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; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
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; SSE41-NEXT: pslld $23, %xmm1
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; SSE41-NEXT: paddd {{.*}}(%rip), %xmm1
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; SSE41-NEXT: cvttps2dq %xmm1, %xmm1
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; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
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; SSE41-NEXT: pmuludq %xmm2, %xmm3
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; SSE41-NEXT: pmuludq %xmm1, %xmm0
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; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
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; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
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; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,0,2,2]
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; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
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; SSE41-NEXT: por %xmm1, %xmm0
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; SSE41-NEXT: movdqa %xmm0, %xmm3
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; SSE41-NEXT: pslld %xmm2, %xmm3
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; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [32,32,32,32]
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; SSE41-NEXT: psubd %xmm1, %xmm2
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; SSE41-NEXT: pmovzxdq {{.*#+}} xmm1 = xmm2[0],zero,xmm2[1],zero
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; SSE41-NEXT: psrld %xmm1, %xmm0
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; SSE41-NEXT: por %xmm3, %xmm0
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; SSE41-NEXT: retq
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;
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; AVX1-LABEL: splatvar_rotate_v4i32:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm2 = xmm1[0],zero,xmm1[1],zero
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; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
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; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
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; AVX1-NEXT: vpslld $23, %xmm1, %xmm1
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; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm1, %xmm1
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; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1
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; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
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; AVX1-NEXT: vpmuludq %xmm3, %xmm2, %xmm2
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; AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
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; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
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; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
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; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vpslld %xmm2, %xmm0, %xmm2
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; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [32,32,32,32]
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; AVX1-NEXT: vpsubd %xmm1, %xmm3, %xmm1
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; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
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; AVX1-NEXT: vpsrld %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vpor %xmm0, %xmm2, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: splatvar_rotate_v4i32:
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@ -922,21 +909,17 @@ define <4 x i32> @splatvar_rotate_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
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;
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; X32-SSE-LABEL: splatvar_rotate_v4i32:
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; X32-SSE: # %bb.0:
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; X32-SSE-NEXT: xorps %xmm2, %xmm2
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; X32-SSE-NEXT: xorps %xmm3, %xmm3
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; X32-SSE-NEXT: movss {{.*#+}} xmm3 = xmm1[0],xmm3[1,2,3]
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; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
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; X32-SSE-NEXT: pslld $23, %xmm1
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; X32-SSE-NEXT: paddd {{\.LCPI.*}}, %xmm1
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; X32-SSE-NEXT: cvttps2dq %xmm1, %xmm1
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; X32-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
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; X32-SSE-NEXT: pmuludq %xmm1, %xmm0
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; X32-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
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; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
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; X32-SSE-NEXT: pmuludq %xmm2, %xmm1
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; X32-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
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; X32-SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
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; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
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; X32-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; X32-SSE-NEXT: por %xmm3, %xmm0
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; X32-SSE-NEXT: movdqa %xmm0, %xmm4
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; X32-SSE-NEXT: pslld %xmm3, %xmm4
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; X32-SSE-NEXT: movdqa {{.*#+}} xmm3 = [32,32,32,32]
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; X32-SSE-NEXT: psubd %xmm1, %xmm3
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; X32-SSE-NEXT: movss {{.*#+}} xmm2 = xmm3[0],xmm2[1,2,3]
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; X32-SSE-NEXT: psrld %xmm2, %xmm0
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; X32-SSE-NEXT: por %xmm4, %xmm0
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; X32-SSE-NEXT: retl
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%splat = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer
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%splat32 = sub <4 x i32> <i32 32, i32 32, i32 32, i32 32>, %splat
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@ -506,29 +506,19 @@ define <4 x i64> @splatvar_rotate_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind {
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define <8 x i32> @splatvar_rotate_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
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; AVX1-LABEL: splatvar_rotate_v8i32:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
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; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
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; AVX1-NEXT: vpslld $23, %xmm1, %xmm1
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; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm1, %xmm1
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; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1
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; AVX1-NEXT: vpshufd {{.*#+}} xmm4 = xmm1[1,1,3,3]
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; AVX1-NEXT: vpmuludq %xmm4, %xmm3, %xmm3
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; AVX1-NEXT: vpmuludq %xmm1, %xmm2, %xmm2
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; AVX1-NEXT: vpshufd {{.*#+}} xmm5 = xmm2[1,1,3,3]
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; AVX1-NEXT: vpblendw {{.*#+}} xmm5 = xmm5[0,1],xmm3[2,3],xmm5[4,5],xmm3[6,7]
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; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[0,0,2,2]
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; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm3[2,3],xmm2[4,5],xmm3[6,7]
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; AVX1-NEXT: vpor %xmm5, %xmm2, %xmm2
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; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
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; AVX1-NEXT: vpmuludq %xmm4, %xmm3, %xmm3
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; AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
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; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
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; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[0,0,2,2]
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm3[2,3],xmm0[4,5],xmm3[6,7]
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; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
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; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[0,0,0,0]
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
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; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
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; AVX1-NEXT: vpslld %xmm1, %xmm3, %xmm4
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; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [32,32,32,32]
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; AVX1-NEXT: vpsubd %xmm2, %xmm5, %xmm2
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; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm2 = xmm2[0],zero,xmm2[1],zero
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; AVX1-NEXT: vpsrld %xmm2, %xmm3, %xmm3
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; AVX1-NEXT: vpor %xmm3, %xmm4, %xmm3
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; AVX1-NEXT: vpslld %xmm1, %xmm0, %xmm1
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; AVX1-NEXT: vpsrld %xmm2, %xmm0, %xmm0
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; AVX1-NEXT: vpor %xmm0, %xmm1, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: splatvar_rotate_v8i32:
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