forked from OSchip/llvm-project
Don't try to create "store atomic" instructions of non-integer types; they aren't supported at the moment. PR12040.
llvm-svn: 152891
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676d3b0682
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@ -942,12 +942,13 @@ RValue CodeGenFunction::EmitBuiltinExpr(const FunctionDecl *FD,
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case Builtin::BI__sync_lock_release_8:
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case Builtin::BI__sync_lock_release_16: {
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Value *Ptr = EmitScalarExpr(E->getArg(0));
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llvm::Type *ElLLVMTy =
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cast<llvm::PointerType>(Ptr->getType())->getElementType();
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llvm::StoreInst *Store =
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Builder.CreateStore(llvm::Constant::getNullValue(ElLLVMTy), Ptr);
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QualType ElTy = E->getArg(0)->getType()->getPointeeType();
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CharUnits StoreSize = getContext().getTypeSizeInChars(ElTy);
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llvm::Type *ITy = llvm::IntegerType::get(getLLVMContext(),
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StoreSize.getQuantity() * 8);
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Ptr = Builder.CreateBitCast(Ptr, ITy->getPointerTo());
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llvm::StoreInst *Store =
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Builder.CreateStore(llvm::Constant::getNullValue(ITy), Ptr);
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Store->setAlignment(StoreSize.getQuantity());
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Store->setAtomic(llvm::Release);
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return RValue::get(0);
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@ -8,6 +8,7 @@ int atomic(void) {
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_Bool valb = 0;
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unsigned int uval = 1;
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int cmp = 0;
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int* ptrval;
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old = __sync_fetch_and_add(&val, 1);
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// CHECK: atomicrmw add i32* %val, i32 1 seq_cst
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@ -75,7 +76,10 @@ int atomic(void) {
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// CHECK: cmpxchg i32* null, i32 0, i32 0 seq_cst
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__sync_lock_release(&val);
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// CHECK: store atomic {{.*}} release, align 4
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// CHECK: store atomic i32 0, {{.*}} release, align 4
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__sync_lock_release(&ptrval);
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// CHECK: store atomic i32 0, {{.*}} release, align 4
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__sync_synchronize ();
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// CHECK: fence seq_cst
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