forked from OSchip/llvm-project
[NFC][GlobalISel]: Add a convenience method to MachineInstrBuilder to simplify getOperand(i).getReg()
https://reviews.llvm.org/D57608 It's a common pattern in GISel to have a MachineInstrBuilder from which we get various regs (commonly MIB->getOperand(0).getReg()). This adds a helper method and the above can be replaced with MIB.getReg(0). llvm-svn: 353223
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@ -79,6 +79,11 @@ public:
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/// explicitly.
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MachineInstr *getInstr() const { return MI; }
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/// Get the register for the operand index.
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/// The operand at the index should be a register (asserted by
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/// MachineOperand).
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unsigned getReg(unsigned Idx) { return MI->getOperand(Idx).getReg(); }
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/// Add a new virtual register operand.
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const MachineInstrBuilder &addReg(unsigned RegNo, unsigned flags = 0,
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unsigned SubReg = 0) const {
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@ -840,7 +840,7 @@ void AArch64InstructionSelector::materializeLargeCMVal(
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constrainSelectedInstRegOperands(*MovI, TII, TRI, RBI);
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return DstReg;
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};
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unsigned DstReg = BuildMovK(MovZ->getOperand(0).getReg(),
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unsigned DstReg = BuildMovK(MovZ.getReg(0),
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AArch64II::MO_G1 | AArch64II::MO_NC, 16, 0);
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DstReg = BuildMovK(DstReg, AArch64II::MO_G2 | AArch64II::MO_NC, 32, 0);
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BuildMovK(DstReg, AArch64II::MO_G3, 48, I.getOperand(0).getReg());
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@ -499,7 +499,7 @@ bool AArch64LegalizerInfo::legalizeVaArg(MachineInstr &MI,
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auto AlignMinus1 = MIRBuilder.buildConstant(IntPtrTy, Align - 1);
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unsigned ListTmp = MRI.createGenericVirtualRegister(PtrTy);
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MIRBuilder.buildGEP(ListTmp, List, AlignMinus1->getOperand(0).getReg());
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MIRBuilder.buildGEP(ListTmp, List, AlignMinus1.getReg(0));
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DstPtr = MRI.createGenericVirtualRegister(PtrTy);
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MIRBuilder.buildPtrMask(DstPtr, ListTmp, Log2_64(Align));
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