forked from OSchip/llvm-project
[PowerPC] [NFC] Create a helper function to copy register to particular register class at PPCFastISel
Make copy register code as common function as following. unsigned copyRegToRegClass(const TargetRegisterClass *ToRC, unsigned SrcReg, unsigned Flag = 0, unsigned SubReg = 0); Differential Revision: https://reviews.llvm.org/D57368 llvm-svn: 352596
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@ -151,6 +151,14 @@ class PPCFastISel final : public FastISel {
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bool isVSSRCRegClass(const TargetRegisterClass *RC) const {
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return RC->getID() == PPC::VSSRCRegClassID;
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}
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unsigned copyRegToRegClass(const TargetRegisterClass *ToRC,
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unsigned SrcReg, unsigned Flag = 0,
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unsigned SubReg = 0) {
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unsigned TmpReg = createResultReg(ToRC);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg, Flag, SubReg);
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return TmpReg;
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}
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bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value,
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bool isZExt, unsigned DestReg,
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const PPC::Predicate Pred);
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@ -877,18 +885,10 @@ bool PPCFastISel::PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2,
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}
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} else {
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CmpOpc = PPC::FCMPUS;
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if (isVSSRCRegClass(RC1)) {
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unsigned TmpReg = createResultReg(&PPC::F4RCRegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg1);
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SrcReg1 = TmpReg;
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}
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if (RC2 && isVSSRCRegClass(RC2)) {
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unsigned TmpReg = createResultReg(&PPC::F4RCRegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg2);
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SrcReg2 = TmpReg;
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}
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if (isVSSRCRegClass(RC1))
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SrcReg1 = copyRegToRegClass(&PPC::F4RCRegClass, SrcReg1);
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if (RC2 && isVSSRCRegClass(RC2))
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SrcReg2 = copyRegToRegClass(&PPC::F4RCRegClass, SrcReg2);
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}
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break;
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case MVT::f64:
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@ -1210,13 +1210,8 @@ bool PPCFastISel::SelectFPToI(const Instruction *I, bool IsSigned) {
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// Convert f32 to f64 if necessary. This is just a meaningless copy
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// to get the register class right.
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const TargetRegisterClass *InRC = MRI.getRegClass(SrcReg);
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if (InRC == &PPC::F4RCRegClass) {
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unsigned TmpReg = createResultReg(&PPC::F8RCRegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::COPY), TmpReg)
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.addReg(SrcReg);
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SrcReg = TmpReg;
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}
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if (InRC == &PPC::F4RCRegClass)
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SrcReg = copyRegToRegClass(&PPC::F8RCRegClass, SrcReg);
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// Determine the opcode for the conversion, which takes place
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// entirely within FPRs.
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@ -1510,11 +1505,7 @@ bool PPCFastISel::finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumByte
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if (RetVT == CopyVT) {
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const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT);
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ResultReg = createResultReg(CpyRC);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::COPY), ResultReg)
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.addReg(SourcePhysReg);
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ResultReg = copyRegToRegClass(CpyRC, SourcePhysReg);
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// If necessary, round the floating result to single precision.
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} else if (CopyVT == MVT::f64) {
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@ -1527,12 +1518,9 @@ bool PPCFastISel::finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumByte
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// used along the fast-isel path (not lowered), and downstream logic
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// also doesn't like a direct subreg copy on a physical reg.)
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} else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) {
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ResultReg = createResultReg(&PPC::GPRCRegClass);
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// Convert physical register from G8RC to GPRC.
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SourcePhysReg -= PPC::X0 - PPC::R0;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::COPY), ResultReg)
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.addReg(SourcePhysReg);
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ResultReg = copyRegToRegClass(&PPC::GPRCRegClass, SourcePhysReg);
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}
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assert(ResultReg && "ResultReg unset!");
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@ -1884,13 +1872,8 @@ bool PPCFastISel::SelectTrunc(const Instruction *I) {
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return false;
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// The only interesting case is when we need to switch register classes.
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if (SrcVT == MVT::i64) {
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unsigned ResultReg = createResultReg(&PPC::GPRCRegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::COPY),
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ResultReg).addReg(SrcReg, 0, PPC::sub_32);
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SrcReg = ResultReg;
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}
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if (SrcVT == MVT::i64)
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SrcReg = copyRegToRegClass(&PPC::GPRCRegClass, SrcReg, 0, PPC::sub_32);
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updateValueMap(I, SrcReg);
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return true;
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