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[PowerPC] [NFC] Create a helper function to copy register to particular register class at PPCFastISel 

Make copy register code as common function as following.

unsigned copyRegToRegClass(const TargetRegisterClass *ToRC, unsigned SrcReg, unsigned Flag = 0, unsigned SubReg = 0);

Differential Revision: https://reviews.llvm.org/D57368

llvm-svn: 352596
This commit is contained in:
Zi Xuan Wu 2019-01-30 02:56:22 +00:00
parent 3933addd30
commit fec749ff5d
1 changed files with 18 additions and 35 deletions
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53
llvm/lib/Target/PowerPC/PPCFastISel.cpp
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@ -151,6 +151,14 @@ class PPCFastISel final : public FastISel {
bool isVSSRCRegClass(const TargetRegisterClass *RC) const { bool isVSSRCRegClass(const TargetRegisterClass *RC) const {
return RC->getID() == PPC::VSSRCRegClassID; return RC->getID() == PPC::VSSRCRegClassID;
} }
unsigned copyRegToRegClass(const TargetRegisterClass *ToRC,
unsigned SrcReg, unsigned Flag = 0,
unsigned SubReg = 0) {
unsigned TmpReg = createResultReg(ToRC);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg, Flag, SubReg);
return TmpReg;
}
bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value, bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value,
bool isZExt, unsigned DestReg, bool isZExt, unsigned DestReg,
const PPC::Predicate Pred); const PPC::Predicate Pred);
@ -877,18 +885,10 @@ bool PPCFastISel::PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2,
} }
} else { } else {
CmpOpc = PPC::FCMPUS; CmpOpc = PPC::FCMPUS;
if (isVSSRCRegClass(RC1)) { if (isVSSRCRegClass(RC1))
unsigned TmpReg = createResultReg(&PPC::F4RCRegClass); SrcReg1 = copyRegToRegClass(&PPC::F4RCRegClass, SrcReg1);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, if (RC2 && isVSSRCRegClass(RC2))
TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg1); SrcReg2 = copyRegToRegClass(&PPC::F4RCRegClass, SrcReg2);
SrcReg1 = TmpReg;
}
if (RC2 && isVSSRCRegClass(RC2)) {
unsigned TmpReg = createResultReg(&PPC::F4RCRegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg2);
SrcReg2 = TmpReg;
}
} }
break; break;
case MVT::f64: case MVT::f64:
@ -1210,13 +1210,8 @@ bool PPCFastISel::SelectFPToI(const Instruction *I, bool IsSigned) {
// Convert f32 to f64 if necessary. This is just a meaningless copy // Convert f32 to f64 if necessary. This is just a meaningless copy
// to get the register class right. // to get the register class right.
const TargetRegisterClass *InRC = MRI.getRegClass(SrcReg); const TargetRegisterClass *InRC = MRI.getRegClass(SrcReg);
if (InRC == &PPC::F4RCRegClass) { if (InRC == &PPC::F4RCRegClass)
unsigned TmpReg = createResultReg(&PPC::F8RCRegClass); SrcReg = copyRegToRegClass(&PPC::F8RCRegClass, SrcReg);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(TargetOpcode::COPY), TmpReg)
.addReg(SrcReg);
SrcReg = TmpReg;
}
// Determine the opcode for the conversion, which takes place // Determine the opcode for the conversion, which takes place
// entirely within FPRs. // entirely within FPRs.
@ -1510,11 +1505,7 @@ bool PPCFastISel::finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumByte
if (RetVT == CopyVT) { if (RetVT == CopyVT) {
const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT); const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT);
ResultReg = createResultReg(CpyRC); ResultReg = copyRegToRegClass(CpyRC, SourcePhysReg);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(TargetOpcode::COPY), ResultReg)
.addReg(SourcePhysReg);
// If necessary, round the floating result to single precision. // If necessary, round the floating result to single precision.
} else if (CopyVT == MVT::f64) { } else if (CopyVT == MVT::f64) {
@ -1527,12 +1518,9 @@ bool PPCFastISel::finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumByte
// used along the fast-isel path (not lowered), and downstream logic // used along the fast-isel path (not lowered), and downstream logic
// also doesn't like a direct subreg copy on a physical reg.) // also doesn't like a direct subreg copy on a physical reg.)
} else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) { } else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) {
ResultReg = createResultReg(&PPC::GPRCRegClass);
// Convert physical register from G8RC to GPRC. // Convert physical register from G8RC to GPRC.
SourcePhysReg -= PPC::X0 - PPC::R0; SourcePhysReg -= PPC::X0 - PPC::R0;
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, ResultReg = copyRegToRegClass(&PPC::GPRCRegClass, SourcePhysReg);
TII.get(TargetOpcode::COPY), ResultReg)
.addReg(SourcePhysReg);
} }
assert(ResultReg && "ResultReg unset!"); assert(ResultReg && "ResultReg unset!");
@ -1884,13 +1872,8 @@ bool PPCFastISel::SelectTrunc(const Instruction *I) {
return false; return false;
// The only interesting case is when we need to switch register classes. // The only interesting case is when we need to switch register classes.
if (SrcVT == MVT::i64) { if (SrcVT == MVT::i64)
unsigned ResultReg = createResultReg(&PPC::GPRCRegClass); SrcReg = copyRegToRegClass(&PPC::GPRCRegClass, SrcReg, 0, PPC::sub_32);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(TargetOpcode::COPY),
ResultReg).addReg(SrcReg, 0, PPC::sub_32);
SrcReg = ResultReg;
}
updateValueMap(I, SrcReg); updateValueMap(I, SrcReg);
return true; return true;