forked from OSchip/llvm-project
[RISCV] Use the commercial name for scheduling model (NFC)
Use the commercial name for the scheduling model for the SiFive 7 Series.
This commit is contained in:
Evandro Menezes
parent
cb9b9842d3
commit
fe9a7d9627
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@ -216,7 +216,7 @@ include "RISCVCallingConv.td"
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include "RISCVInstrInfo.td"
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include "RISCVRegisterBanks.td"
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include "RISCVSchedRocket.td"
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include "RISCVSchedBullet.td"
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include "RISCVSchedSiFive7.td"
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//===----------------------------------------------------------------------===//
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// RISC-V processors supported.
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@ -228,8 +228,8 @@ def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
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def : ProcessorModel<"rocket-rv32", RocketModel, []>;
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def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>;
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def : ProcessorModel<"sifive-7-rv32", BulletModel, []>;
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def : ProcessorModel<"sifive-7-rv64", BulletModel, [Feature64Bit]>;
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def : ProcessorModel<"sifive-7-rv32", SiFive7Model, []>;
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def : ProcessorModel<"sifive-7-rv64", SiFive7Model, [Feature64Bit]>;
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def : ProcessorModel<"sifive-e31", RocketModel, [FeatureStdExtM,
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FeatureStdExtA,
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@ -242,17 +242,17 @@ def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,
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FeatureStdExtD,
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FeatureStdExtC]>;
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def : ProcessorModel<"sifive-e76", BulletModel, [FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtC]>;
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def : ProcessorModel<"sifive-e76", SiFive7Model, [FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtC]>;
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def : ProcessorModel<"sifive-u74", BulletModel, [Feature64Bit,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC]>;
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def : ProcessorModel<"sifive-u74", SiFive7Model, [Feature64Bit,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC]>;
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//===----------------------------------------------------------------------===//
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// Define the RISC-V target.
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@ -1,224 +0,0 @@
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//==- RISCVSchedBullet.td - Bullet Scheduling Definitions ----*- tablegen -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// The following definitions describe the simpler per-operand machine model.
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// This works with MachineScheduler. See MCSchedule.h for details.
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// Bullet machine model for scheduling and other instruction cost heuristics.
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def BulletModel : SchedMachineModel {
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let MicroOpBufferSize = 0; // Explicitly set to zero since Bullet is in-order.
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let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
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let LoadLatency = 3;
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let MispredictPenalty = 3;
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let CompleteModel = 0;
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let UnsupportedFeatures = [HasStdExtV, HasStdExtZvamo, HasStdExtZvlsseg];
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}
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// The Bullet microarchitecure has two pipelines: A and B.
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// Pipe A can handle memory, integer alu and vector operations.
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// Pipe B can handle integer alu, control flow, integer multiply and divide,
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// and floating point computation.
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let SchedModel = BulletModel in {
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let BufferSize = 0 in {
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def BulletPipeA : ProcResource<1>;
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def BulletPipeB : ProcResource<1>;
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}
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let BufferSize = 1 in {
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def BulletIDiv : ProcResource<1> { let Super = BulletPipeB; } // Int Division
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def BulletFDiv : ProcResource<1> { let Super = BulletPipeB; } // FP Division/Sqrt
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}
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def BulletPipeAB : ProcResGroup<[BulletPipeA, BulletPipeB]>;
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// Branching
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def : WriteRes<WriteJmp, [BulletPipeB]>;
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def : WriteRes<WriteJal, [BulletPipeB]>;
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def : WriteRes<WriteJalr, [BulletPipeB]>;
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def : WriteRes<WriteJmpReg, [BulletPipeB]>;
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// Integer arithmetic and logic
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let Latency = 3 in {
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def : WriteRes<WriteIALU, [BulletPipeAB]>;
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def : WriteRes<WriteIALU32, [BulletPipeAB]>;
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def : WriteRes<WriteShift, [BulletPipeAB]>;
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def : WriteRes<WriteShift32, [BulletPipeAB]>;
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}
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// Integer multiplication
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let Latency = 3 in {
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def : WriteRes<WriteIMul, [BulletPipeB]>;
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def : WriteRes<WriteIMul32, [BulletPipeB]>;
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}
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// Integer division
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def : WriteRes<WriteIDiv, [BulletPipeB, BulletIDiv]> {
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let Latency = 16;
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let ResourceCycles = [1, 15];
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}
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def : WriteRes<WriteIDiv32, [BulletPipeB, BulletIDiv]> {
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let Latency = 16;
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let ResourceCycles = [1, 15];
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}
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// Memory
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def : WriteRes<WriteSTB, [BulletPipeA]>;
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def : WriteRes<WriteSTH, [BulletPipeA]>;
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def : WriteRes<WriteSTW, [BulletPipeA]>;
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def : WriteRes<WriteSTD, [BulletPipeA]>;
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def : WriteRes<WriteFST32, [BulletPipeA]>;
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def : WriteRes<WriteFST64, [BulletPipeA]>;
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let Latency = 3 in {
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def : WriteRes<WriteLDB, [BulletPipeA]>;
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def : WriteRes<WriteLDH, [BulletPipeA]>;
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def : WriteRes<WriteLDW, [BulletPipeA]>;
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def : WriteRes<WriteLDWU, [BulletPipeA]>;
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def : WriteRes<WriteLDD, [BulletPipeA]>;
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}
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let Latency = 2 in {
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def : WriteRes<WriteFLD32, [BulletPipeA]>;
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def : WriteRes<WriteFLD64, [BulletPipeA]>;
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}
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// Atomic memory
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def : WriteRes<WriteAtomicSTW, [BulletPipeA]>;
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def : WriteRes<WriteAtomicSTD, [BulletPipeA]>;
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let Latency = 3 in {
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def : WriteRes<WriteAtomicW, [BulletPipeA]>;
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def : WriteRes<WriteAtomicD, [BulletPipeA]>;
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def : WriteRes<WriteAtomicLDW, [BulletPipeA]>;
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def : WriteRes<WriteAtomicLDD, [BulletPipeA]>;
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}
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// Single precision.
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let Latency = 5 in {
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def : WriteRes<WriteFALU32, [BulletPipeB]>;
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def : WriteRes<WriteFMul32, [BulletPipeB]>;
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def : WriteRes<WriteFMulAdd32, [BulletPipeB]>;
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def : WriteRes<WriteFMulSub32, [BulletPipeB]>;
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}
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let Latency = 3 in {
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def : WriteRes<WriteFSGNJ32, [BulletPipeB]>;
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def : WriteRes<WriteFMinMax32, [BulletPipeB]>;
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}
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def : WriteRes<WriteFDiv32, [BulletPipeB, BulletFDiv]> { let Latency = 27;
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let ResourceCycles = [1, 26]; }
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def : WriteRes<WriteFSqrt32, [BulletPipeB, BulletFDiv]> { let Latency = 27;
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let ResourceCycles = [1, 26]; }
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// Double precision
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let Latency = 7 in {
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def : WriteRes<WriteFALU64, [BulletPipeB]>;
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def : WriteRes<WriteFMul64, [BulletPipeB]>;
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def : WriteRes<WriteFMulAdd64, [BulletPipeB]>;
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def : WriteRes<WriteFMulSub64, [BulletPipeB]>;
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}
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let Latency = 3 in {
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def : WriteRes<WriteFSGNJ64, [BulletPipeB]>;
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def : WriteRes<WriteFMinMax64, [BulletPipeB]>;
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}
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def : WriteRes<WriteFDiv64, [BulletPipeB, BulletFDiv]> { let Latency = 56;
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let ResourceCycles = [1, 55]; }
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def : WriteRes<WriteFSqrt64, [BulletPipeB, BulletFDiv]> { let Latency = 56;
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let ResourceCycles = [1, 55]; }
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// Conversions
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let Latency = 3 in {
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def : WriteRes<WriteFCvtI32ToF32, [BulletPipeB]>;
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def : WriteRes<WriteFCvtI32ToF64, [BulletPipeB]>;
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def : WriteRes<WriteFCvtI64ToF32, [BulletPipeB]>;
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def : WriteRes<WriteFCvtI64ToF64, [BulletPipeB]>;
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def : WriteRes<WriteFCvtF32ToI32, [BulletPipeB]>;
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def : WriteRes<WriteFCvtF32ToI64, [BulletPipeB]>;
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def : WriteRes<WriteFCvtF32ToF64, [BulletPipeB]>;
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def : WriteRes<WriteFCvtF64ToI32, [BulletPipeB]>;
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def : WriteRes<WriteFCvtF64ToI64, [BulletPipeB]>;
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def : WriteRes<WriteFCvtF64ToF32, [BulletPipeB]>;
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def : WriteRes<WriteFClass32, [BulletPipeB]>;
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def : WriteRes<WriteFClass64, [BulletPipeB]>;
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def : WriteRes<WriteFCmp32, [BulletPipeB]>;
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def : WriteRes<WriteFCmp64, [BulletPipeB]>;
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def : WriteRes<WriteFMovI32ToF32, [BulletPipeB]>;
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def : WriteRes<WriteFMovF32ToI32, [BulletPipeB]>;
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def : WriteRes<WriteFMovI64ToF64, [BulletPipeB]>;
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def : WriteRes<WriteFMovF64ToI64, [BulletPipeB]>;
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}
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// Others
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def : WriteRes<WriteCSR, [BulletPipeB]>;
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def : WriteRes<WriteNop, []>;
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def : InstRW<[WriteIALU], (instrs COPY)>;
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//===----------------------------------------------------------------------===//
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// Bypass and advance
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def : ReadAdvance<ReadJmp, 0>;
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def : ReadAdvance<ReadJalr, 0>;
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def : ReadAdvance<ReadCSR, 0>;
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def : ReadAdvance<ReadStoreData, 0>;
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def : ReadAdvance<ReadMemBase, 0>;
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def : ReadAdvance<ReadIALU, 0>;
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def : ReadAdvance<ReadIALU32, 0>;
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def : ReadAdvance<ReadShift, 0>;
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def : ReadAdvance<ReadShift32, 0>;
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def : ReadAdvance<ReadIDiv, 0>;
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def : ReadAdvance<ReadIDiv32, 0>;
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def : ReadAdvance<ReadIMul, 0>;
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def : ReadAdvance<ReadIMul32, 0>;
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def : ReadAdvance<ReadAtomicWA, 0>;
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def : ReadAdvance<ReadAtomicWD, 0>;
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def : ReadAdvance<ReadAtomicDA, 0>;
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def : ReadAdvance<ReadAtomicDD, 0>;
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def : ReadAdvance<ReadAtomicLDW, 0>;
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def : ReadAdvance<ReadAtomicLDD, 0>;
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def : ReadAdvance<ReadAtomicSTW, 0>;
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def : ReadAdvance<ReadAtomicSTD, 0>;
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def : ReadAdvance<ReadFMemBase, 0>;
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def : ReadAdvance<ReadFALU32, 0>;
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def : ReadAdvance<ReadFALU64, 0>;
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def : ReadAdvance<ReadFMul32, 0>;
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def : ReadAdvance<ReadFMulAdd32, 0>;
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def : ReadAdvance<ReadFMulSub32, 0>;
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def : ReadAdvance<ReadFMul64, 0>;
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def : ReadAdvance<ReadFMulAdd64, 0>;
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def : ReadAdvance<ReadFMulSub64, 0>;
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def : ReadAdvance<ReadFDiv32, 0>;
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def : ReadAdvance<ReadFDiv64, 0>;
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def : ReadAdvance<ReadFSqrt32, 0>;
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def : ReadAdvance<ReadFSqrt64, 0>;
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def : ReadAdvance<ReadFCmp32, 0>;
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def : ReadAdvance<ReadFCmp64, 0>;
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def : ReadAdvance<ReadFSGNJ32, 0>;
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def : ReadAdvance<ReadFSGNJ64, 0>;
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def : ReadAdvance<ReadFMinMax32, 0>;
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def : ReadAdvance<ReadFMinMax64, 0>;
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def : ReadAdvance<ReadFCvtF32ToI32, 0>;
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def : ReadAdvance<ReadFCvtF32ToI64, 0>;
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def : ReadAdvance<ReadFCvtF64ToI32, 0>;
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def : ReadAdvance<ReadFCvtF64ToI64, 0>;
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def : ReadAdvance<ReadFCvtI32ToF32, 0>;
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def : ReadAdvance<ReadFCvtI32ToF64, 0>;
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def : ReadAdvance<ReadFCvtI64ToF32, 0>;
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def : ReadAdvance<ReadFCvtI64ToF64, 0>;
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def : ReadAdvance<ReadFCvtF32ToF64, 0>;
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def : ReadAdvance<ReadFCvtF64ToF32, 0>;
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def : ReadAdvance<ReadFMovF32ToI32, 0>;
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def : ReadAdvance<ReadFMovI32ToF32, 0>;
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def : ReadAdvance<ReadFMovF64ToI64, 0>;
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def : ReadAdvance<ReadFMovI64ToF64, 0>;
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def : ReadAdvance<ReadFClass32, 0>;
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def : ReadAdvance<ReadFClass64, 0>;
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}
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@ -0,0 +1,222 @@
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//==- RISCVSchedSiFive7.td - SiFive7 Scheduling Definitions --*- tablegen -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// SiFive7 machine model for scheduling and other instruction cost heuristics.
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def SiFive7Model : SchedMachineModel {
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let MicroOpBufferSize = 0; // Explicitly set to zero since SiFive7 is in-order.
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let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
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let LoadLatency = 3;
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let MispredictPenalty = 3;
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let CompleteModel = 0;
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let UnsupportedFeatures = [HasStdExtV, HasStdExtZvamo, HasStdExtZvlsseg];
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}
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// The SiFive7 microarchitecure has two pipelines: A and B.
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// Pipe A can handle memory, integer alu and vector operations.
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// Pipe B can handle integer alu, control flow, integer multiply and divide,
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// and floating point computation.
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let SchedModel = SiFive7Model in {
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let BufferSize = 0 in {
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def SiFive7PipeA : ProcResource<1>;
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def SiFive7PipeB : ProcResource<1>;
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}
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let BufferSize = 1 in {
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def SiFive7IDiv : ProcResource<1> { let Super = SiFive7PipeB; } // Int Division
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def SiFive7FDiv : ProcResource<1> { let Super = SiFive7PipeB; } // FP Division/Sqrt
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}
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def SiFive7PipeAB : ProcResGroup<[SiFive7PipeA, SiFive7PipeB]>;
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// Branching
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def : WriteRes<WriteJmp, [SiFive7PipeB]>;
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def : WriteRes<WriteJal, [SiFive7PipeB]>;
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def : WriteRes<WriteJalr, [SiFive7PipeB]>;
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def : WriteRes<WriteJmpReg, [SiFive7PipeB]>;
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// Integer arithmetic and logic
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let Latency = 3 in {
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def : WriteRes<WriteIALU, [SiFive7PipeAB]>;
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def : WriteRes<WriteIALU32, [SiFive7PipeAB]>;
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def : WriteRes<WriteShift, [SiFive7PipeAB]>;
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def : WriteRes<WriteShift32, [SiFive7PipeAB]>;
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}
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// Integer multiplication
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let Latency = 3 in {
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def : WriteRes<WriteIMul, [SiFive7PipeB]>;
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def : WriteRes<WriteIMul32, [SiFive7PipeB]>;
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}
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// Integer division
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def : WriteRes<WriteIDiv, [SiFive7PipeB, SiFive7IDiv]> {
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let Latency = 16;
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let ResourceCycles = [1, 15];
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}
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def : WriteRes<WriteIDiv32, [SiFive7PipeB, SiFive7IDiv]> {
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let Latency = 16;
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let ResourceCycles = [1, 15];
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}
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// Memory
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def : WriteRes<WriteSTB, [SiFive7PipeA]>;
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def : WriteRes<WriteSTH, [SiFive7PipeA]>;
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def : WriteRes<WriteSTW, [SiFive7PipeA]>;
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def : WriteRes<WriteSTD, [SiFive7PipeA]>;
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def : WriteRes<WriteFST32, [SiFive7PipeA]>;
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def : WriteRes<WriteFST64, [SiFive7PipeA]>;
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let Latency = 3 in {
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def : WriteRes<WriteLDB, [SiFive7PipeA]>;
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def : WriteRes<WriteLDH, [SiFive7PipeA]>;
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def : WriteRes<WriteLDW, [SiFive7PipeA]>;
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def : WriteRes<WriteLDWU, [SiFive7PipeA]>;
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def : WriteRes<WriteLDD, [SiFive7PipeA]>;
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}
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let Latency = 2 in {
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def : WriteRes<WriteFLD32, [SiFive7PipeA]>;
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def : WriteRes<WriteFLD64, [SiFive7PipeA]>;
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}
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// Atomic memory
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def : WriteRes<WriteAtomicSTW, [SiFive7PipeA]>;
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def : WriteRes<WriteAtomicSTD, [SiFive7PipeA]>;
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let Latency = 3 in {
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def : WriteRes<WriteAtomicW, [SiFive7PipeA]>;
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def : WriteRes<WriteAtomicD, [SiFive7PipeA]>;
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def : WriteRes<WriteAtomicLDW, [SiFive7PipeA]>;
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def : WriteRes<WriteAtomicLDD, [SiFive7PipeA]>;
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}
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// Single precision.
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let Latency = 5 in {
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def : WriteRes<WriteFALU32, [SiFive7PipeB]>;
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def : WriteRes<WriteFMul32, [SiFive7PipeB]>;
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def : WriteRes<WriteFMulAdd32, [SiFive7PipeB]>;
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def : WriteRes<WriteFMulSub32, [SiFive7PipeB]>;
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}
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let Latency = 3 in {
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def : WriteRes<WriteFSGNJ32, [SiFive7PipeB]>;
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def : WriteRes<WriteFMinMax32, [SiFive7PipeB]>;
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}
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def : WriteRes<WriteFDiv32, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 27;
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let ResourceCycles = [1, 26]; }
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def : WriteRes<WriteFSqrt32, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 27;
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let ResourceCycles = [1, 26]; }
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// Double precision
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let Latency = 7 in {
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def : WriteRes<WriteFALU64, [SiFive7PipeB]>;
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def : WriteRes<WriteFMul64, [SiFive7PipeB]>;
|
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def : WriteRes<WriteFMulAdd64, [SiFive7PipeB]>;
|
||||
def : WriteRes<WriteFMulSub64, [SiFive7PipeB]>;
|
||||
}
|
||||
let Latency = 3 in {
|
||||
def : WriteRes<WriteFSGNJ64, [SiFive7PipeB]>;
|
||||
def : WriteRes<WriteFMinMax64, [SiFive7PipeB]>;
|
||||
}
|
||||
|
||||
def : WriteRes<WriteFDiv64, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 56;
|
||||
let ResourceCycles = [1, 55]; }
|
||||
def : WriteRes<WriteFSqrt64, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 56;
|
||||
let ResourceCycles = [1, 55]; }
|
||||
|
||||
// Conversions
|
||||
let Latency = 3 in {
|
||||
def : WriteRes<WriteFCvtI32ToF32, [SiFive7PipeB]>;
|
||||
def : WriteRes<WriteFCvtI32ToF64, [SiFive7PipeB]>;
|
||||
def : WriteRes<WriteFCvtI64ToF32, [SiFive7PipeB]>;
|
||||
def : WriteRes<WriteFCvtI64ToF64, [SiFive7PipeB]>;
|
||||
def : WriteRes<WriteFCvtF32ToI32, [SiFive7PipeB]>;
|
||||
def : WriteRes<WriteFCvtF32ToI64, [SiFive7PipeB]>;
|
||||
def : WriteRes<WriteFCvtF32ToF64, [SiFive7PipeB]>;
|
||||
def : WriteRes<WriteFCvtF64ToI32, [SiFive7PipeB]>;
|
||||
def : WriteRes<WriteFCvtF64ToI64, [SiFive7PipeB]>;
|
||||
def : WriteRes<WriteFCvtF64ToF32, [SiFive7PipeB]>;
|
||||
|
||||
def : WriteRes<WriteFClass32, [SiFive7PipeB]>;
|
||||
def : WriteRes<WriteFClass64, [SiFive7PipeB]>;
|
||||
def : WriteRes<WriteFCmp32, [SiFive7PipeB]>;
|
||||
def : WriteRes<WriteFCmp64, [SiFive7PipeB]>;
|
||||
def : WriteRes<WriteFMovI32ToF32, [SiFive7PipeB]>;
|
||||
def : WriteRes<WriteFMovF32ToI32, [SiFive7PipeB]>;
|
||||
def : WriteRes<WriteFMovI64ToF64, [SiFive7PipeB]>;
|
||||
def : WriteRes<WriteFMovF64ToI64, [SiFive7PipeB]>;
|
||||
}
|
||||
|
||||
// Others
|
||||
def : WriteRes<WriteCSR, [SiFive7PipeB]>;
|
||||
def : WriteRes<WriteNop, []>;
|
||||
|
||||
def : InstRW<[WriteIALU], (instrs COPY)>;
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Bypass and advance
|
||||
def : ReadAdvance<ReadJmp, 0>;
|
||||
def : ReadAdvance<ReadJalr, 0>;
|
||||
def : ReadAdvance<ReadCSR, 0>;
|
||||
def : ReadAdvance<ReadStoreData, 0>;
|
||||
def : ReadAdvance<ReadMemBase, 0>;
|
||||
def : ReadAdvance<ReadIALU, 0>;
|
||||
def : ReadAdvance<ReadIALU32, 0>;
|
||||
def : ReadAdvance<ReadShift, 0>;
|
||||
def : ReadAdvance<ReadShift32, 0>;
|
||||
def : ReadAdvance<ReadIDiv, 0>;
|
||||
def : ReadAdvance<ReadIDiv32, 0>;
|
||||
def : ReadAdvance<ReadIMul, 0>;
|
||||
def : ReadAdvance<ReadIMul32, 0>;
|
||||
def : ReadAdvance<ReadAtomicWA, 0>;
|
||||
def : ReadAdvance<ReadAtomicWD, 0>;
|
||||
def : ReadAdvance<ReadAtomicDA, 0>;
|
||||
def : ReadAdvance<ReadAtomicDD, 0>;
|
||||
def : ReadAdvance<ReadAtomicLDW, 0>;
|
||||
def : ReadAdvance<ReadAtomicLDD, 0>;
|
||||
def : ReadAdvance<ReadAtomicSTW, 0>;
|
||||
def : ReadAdvance<ReadAtomicSTD, 0>;
|
||||
def : ReadAdvance<ReadFMemBase, 0>;
|
||||
def : ReadAdvance<ReadFALU32, 0>;
|
||||
def : ReadAdvance<ReadFALU64, 0>;
|
||||
def : ReadAdvance<ReadFMul32, 0>;
|
||||
def : ReadAdvance<ReadFMulAdd32, 0>;
|
||||
def : ReadAdvance<ReadFMulSub32, 0>;
|
||||
def : ReadAdvance<ReadFMul64, 0>;
|
||||
def : ReadAdvance<ReadFMulAdd64, 0>;
|
||||
def : ReadAdvance<ReadFMulSub64, 0>;
|
||||
def : ReadAdvance<ReadFDiv32, 0>;
|
||||
def : ReadAdvance<ReadFDiv64, 0>;
|
||||
def : ReadAdvance<ReadFSqrt32, 0>;
|
||||
def : ReadAdvance<ReadFSqrt64, 0>;
|
||||
def : ReadAdvance<ReadFCmp32, 0>;
|
||||
def : ReadAdvance<ReadFCmp64, 0>;
|
||||
def : ReadAdvance<ReadFSGNJ32, 0>;
|
||||
def : ReadAdvance<ReadFSGNJ64, 0>;
|
||||
def : ReadAdvance<ReadFMinMax32, 0>;
|
||||
def : ReadAdvance<ReadFMinMax64, 0>;
|
||||
def : ReadAdvance<ReadFCvtF32ToI32, 0>;
|
||||
def : ReadAdvance<ReadFCvtF32ToI64, 0>;
|
||||
def : ReadAdvance<ReadFCvtF64ToI32, 0>;
|
||||
def : ReadAdvance<ReadFCvtF64ToI64, 0>;
|
||||
def : ReadAdvance<ReadFCvtI32ToF32, 0>;
|
||||
def : ReadAdvance<ReadFCvtI32ToF64, 0>;
|
||||
def : ReadAdvance<ReadFCvtI64ToF32, 0>;
|
||||
def : ReadAdvance<ReadFCvtI64ToF64, 0>;
|
||||
def : ReadAdvance<ReadFCvtF32ToF64, 0>;
|
||||
def : ReadAdvance<ReadFCvtF64ToF32, 0>;
|
||||
def : ReadAdvance<ReadFMovF32ToI32, 0>;
|
||||
def : ReadAdvance<ReadFMovI32ToF32, 0>;
|
||||
def : ReadAdvance<ReadFMovF64ToI64, 0>;
|
||||
def : ReadAdvance<ReadFMovI64ToF64, 0>;
|
||||
def : ReadAdvance<ReadFClass32, 0>;
|
||||
def : ReadAdvance<ReadFClass64, 0>;
|
||||
}
|
||||
Loading…
Reference in New Issue