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AMDGPU: Generate test checks

This commit is contained in:
Matt Arsenault 2020-01-24 21:59:48 -05:00 committed by Matt Arsenault
parent 86c944d790
commit fe9765762c
2 changed files with 284 additions and 130 deletions
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207
llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
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@ -1,77 +1,154 @@
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI,SIVI %s ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SIVI,VI,VIGFX9 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX6 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,VIGFX9 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX8 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
declare half @llvm.cos.f16(half %a) define amdgpu_kernel void @cos_f16(half addrspace(1)* %r, half addrspace(1)* %a) {
declare <2 x half> @llvm.cos.v2f16(<2 x half> %a) ; GFX6-LABEL: cos_f16:
; GFX6: ; %bb.0:
; GCN-LABEL: {{^}}cos_f16 ; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]] ; GFX6-NEXT: s_mov_b32 s2, -1
; GCN: v_mul_f32_e32 v[[M_F32:[0-9]+]], {{0.15915494|0x3e22f983}}, v[[A_F32]] ; GFX6-NEXT: s_mov_b32 s10, s2
; SIVI: v_fract_f32_e32 v[[F_F32:[0-9]+]], v[[M_F32]] ; GFX6-NEXT: s_mov_b32 s11, s3
; SIVI: v_cos_f32_e32 v[[R_F32:[0-9]+]], v[[F_F32]] ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NOT: v_fract_f32 ; GFX6-NEXT: s_mov_b32 s8, s6
; GFX9: v_cos_f32_e32 v[[R_F32:[0-9]+]], v[[M_F32]] ; GFX6-NEXT: s_mov_b32 s9, s7
; GCN: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]] ; GFX6-NEXT: buffer_load_ushort v0, off, s[8:11], 0
; GCN: buffer_store_short v[[R_F16]] ; GFX6-NEXT: s_mov_b32 s0, s4
; GCN: s_endpgm ; GFX6-NEXT: s_mov_b32 s1, s5
define amdgpu_kernel void @cos_f16( ; GFX6-NEXT: s_waitcnt vmcnt(0)
half addrspace(1)* %r, ; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
half addrspace(1)* %a) { ; GFX6-NEXT: v_mul_f32_e32 v0, 0x3e22f983, v0
entry: ; GFX6-NEXT: v_fract_f32_e32 v0, v0
; GFX6-NEXT: v_cos_f32_e32 v0, v0
; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX6-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
;
; GFX8-LABEL: cos_f16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: flat_load_ushort v0, v[0:1]
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX8-NEXT: v_mul_f32_e32 v0, 0.15915494, v0
; GFX8-NEXT: v_fract_f32_e32 v0, v0
; GFX8-NEXT: v_cos_f32_e32 v0, v0
; GFX8-NEXT: v_cvt_f16_f32_e32 v2, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: flat_store_short v[0:1], v2
; GFX8-NEXT: s_endpgm
;
; GFX9-LABEL: cos_f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: global_load_ushort v0, v[0:1], off
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v0, 0.15915494, v0
; GFX9-NEXT: v_cos_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v0
; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: global_store_short v[0:1], v2, off
; GFX9-NEXT: s_endpgm
%a.val = load half, half addrspace(1)* %a %a.val = load half, half addrspace(1)* %a
%r.val = call half @llvm.cos.f16(half %a.val) %r.val = call half @llvm.cos.f16(half %a.val)
store half %r.val, half addrspace(1)* %r store half %r.val, half addrspace(1)* %r
ret void ret void
} }
; GCN-LABEL: {{^}}cos_v2f16: define amdgpu_kernel void @cos_v2f16(<2 x half> addrspace(1)* %r, <2 x half> addrspace(1)* %a) {
; GCN-DAG: buffer_load_dword v[[A_V2_F16:[0-9]+]] ; GFX6-LABEL: cos_v2f16:
; GFX6: ; %bb.0:
; SI-DAG: s_mov_b32 [[HALF_PI:s[0-9]+]], 0x3e22f983{{$}} ; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]] ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] ; GFX6-NEXT: s_mov_b32 s2, -1
; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]] ; GFX6-NEXT: s_mov_b32 s10, s2
; SI: v_mul_f32_e32 v[[M_F32_0:[0-9]+]], [[HALF_PI]], v[[A_F32_0]] ; GFX6-NEXT: s_mov_b32 s11, s3
; SI: v_fract_f32_e32 v[[F_F32_0:[0-9]+]], v[[M_F32_0]] ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; SI: v_mul_f32_e32 v[[M_F32_1:[0-9]+]], [[HALF_PI]], v[[A_F32_1]] ; GFX6-NEXT: s_mov_b32 s8, s6
; SI: v_fract_f32_e32 v[[F_F32_1:[0-9]+]], v[[M_F32_1]] ; GFX6-NEXT: s_mov_b32 s9, s7
; SI: v_cos_f32_e32 v[[R_F32_1:[0-9]+]], v[[F_F32_1]] ; GFX6-NEXT: buffer_load_dword v0, off, s[8:11], 0
; SI: v_cos_f32_e32 v[[R_F32_0:[0-9]+]], v[[F_F32_0]] ; GFX6-NEXT: s_mov_b32 s0, 0x3e22f983
; SI: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]] ; GFX6-NEXT: s_mov_b32 s1, s5
; GFX6-NEXT: s_waitcnt vmcnt(0)
; VIGFX9-DAG: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]] ; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v0
; VIGFX9-DAG: v_cvt_f32_f16_sdwa v[[A_F32_1:[0-9]+]], v[[A_V2_F16]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; VIGFX9-DAG: v_mul_f32_e32 v[[M_F32_0:[0-9]+]], 0.15915494, v[[A_F32_0]] ; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
; VIGFX9-DAG: v_mul_f32_e32 v[[M_F32_1:[0-9]+]], 0.15915494, v[[A_F32_1]] ; GFX6-NEXT: v_mul_f32_e32 v1, s0, v1
; VI-DAG: v_fract_f32_e32 v[[F_F32_0:[0-9]+]], v[[M_F32_0]] ; GFX6-NEXT: v_fract_f32_e32 v1, v1
; VI-DAG: v_fract_f32_e32 v[[F_F32_1:[0-9]+]], v[[M_F32_1]] ; GFX6-NEXT: v_mul_f32_e32 v0, s0, v0
; VI-DAG: v_cos_f32_e32 v[[R_F32_1:[0-9]+]], v[[F_F32_1]] ; GFX6-NEXT: v_fract_f32_e32 v0, v0
; VI-DAG: v_cos_f32_e32 v[[R_F32_0:[0-9]+]], v[[F_F32_0]] ; GFX6-NEXT: v_cos_f32_e32 v0, v0
; GFX9-DAG: v_cos_f32_e32 v[[R_F32_1:[0-9]+]], v[[M_F32_1]] ; GFX6-NEXT: v_cos_f32_e32 v1, v1
; GFX9-DAG: v_cos_f32_e32 v[[R_F32_0:[0-9]+]], v[[M_F32_0]] ; GFX6-NEXT: s_mov_b32 s0, s4
; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
; GCN-DAG: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]] ; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] ; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]] ; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
; VI-DAG: v_cvt_f16_f32_sdwa v[[R_F16_1:[0-9]+]], v[[R_F32_1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD ;
; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_1]] ; GFX8-LABEL: cos_v2f16:
; GFX8: ; %bb.0:
; GFX9-DAG: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]] ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-DAG: v_and_b32_e32 v[[R2_F16_0:[0-9]+]], 0xffff, v[[R_F16_0]] ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DAG: v_lshl_or_b32 v[[R_V2_F16:[0-9]+]], v[[R_F16_1]], 16, v[[R2_F16_0]] ; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GCN: buffer_store_dword v[[R_V2_F16]] ; GFX8-NEXT: flat_load_dword v0, v[0:1]
; GCN: s_endpgm ; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
define amdgpu_kernel void @cos_v2f16( ; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
<2 x half> addrspace(1)* %r, ; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0
<2 x half> addrspace(1)* %a) { ; GFX8-NEXT: v_mul_f32_e32 v1, 0.15915494, v1
entry: ; GFX8-NEXT: v_mul_f32_e32 v0, 0.15915494, v0
; GFX8-NEXT: v_fract_f32_e32 v1, v1
; GFX8-NEXT: v_fract_f32_e32 v0, v0
; GFX8-NEXT: v_cos_f32_e32 v1, v1
; GFX8-NEXT: v_cos_f32_e32 v0, v0
; GFX8-NEXT: v_cvt_f16_f32_sdwa v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
; GFX8-NEXT: v_cvt_f16_f32_e32 v3, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_or_b32_e32 v2, v3, v2
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
;
; GFX9-LABEL: cos_v2f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: global_load_dword v0, v[0:1], off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v0
; GFX9-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-NEXT: v_mul_f32_e32 v1, 0.15915494, v1
; GFX9-NEXT: v_mul_f32_e32 v0, 0.15915494, v0
; GFX9-NEXT: v_cos_f32_e32 v1, v1
; GFX9-NEXT: v_cos_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v1
; GFX9-NEXT: v_cvt_f16_f32_e32 v3, v0
; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_endpgm
%a.val = load <2 x half>, <2 x half> addrspace(1)* %a %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
%r.val = call <2 x half> @llvm.cos.v2f16(<2 x half> %a.val) %r.val = call <2 x half> @llvm.cos.v2f16(<2 x half> %a.val)
store <2 x half> %r.val, <2 x half> addrspace(1)* %r store <2 x half> %r.val, <2 x half> addrspace(1)* %r
ret void ret void
} }
declare half @llvm.cos.f16(half %a)
declare <2 x half> @llvm.cos.v2f16(<2 x half> %a)

207
llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
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@ -1,77 +1,154 @@
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SIVI,SI %s ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SIVI,VI,VIGFX9 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX6 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,VIGFX9 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX8 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
declare half @llvm.sin.f16(half %a) define amdgpu_kernel void @sin_f16(half addrspace(1)* %r, half addrspace(1)* %a) {
declare <2 x half> @llvm.sin.v2f16(<2 x half> %a) ; GFX6-LABEL: sin_f16:
; GFX6: ; %bb.0:
; GCN-LABEL: {{^}}sin_f16: ; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]] ; GFX6-NEXT: s_mov_b32 s2, -1
; GCN: v_mul_f32_e32 v[[M_F32:[0-9]+]], {{0.15915494|0x3e22f983}}, v[[A_F32]] ; GFX6-NEXT: s_mov_b32 s10, s2
; SIVI: v_fract_f32_e32 v[[F_F32:[0-9]+]], v[[M_F32]] ; GFX6-NEXT: s_mov_b32 s11, s3
; SIVI: v_sin_f32_e32 v[[R_F32:[0-9]+]], v[[F_F32]] ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NOT: v_fract_f32_e32 ; GFX6-NEXT: s_mov_b32 s8, s6
; GFX9: v_sin_f32_e32 v[[R_F32:[0-9]+]], v[[M_F32]] ; GFX6-NEXT: s_mov_b32 s9, s7
; GCN: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]] ; GFX6-NEXT: buffer_load_ushort v0, off, s[8:11], 0
; GCN: buffer_store_short v[[R_F16]] ; GFX6-NEXT: s_mov_b32 s0, s4
; GCN: s_endpgm ; GFX6-NEXT: s_mov_b32 s1, s5
define amdgpu_kernel void @sin_f16( ; GFX6-NEXT: s_waitcnt vmcnt(0)
half addrspace(1)* %r, ; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
half addrspace(1)* %a) { ; GFX6-NEXT: v_mul_f32_e32 v0, 0x3e22f983, v0
entry: ; GFX6-NEXT: v_fract_f32_e32 v0, v0
; GFX6-NEXT: v_sin_f32_e32 v0, v0
; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX6-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
;
; GFX8-LABEL: sin_f16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: flat_load_ushort v0, v[0:1]
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX8-NEXT: v_mul_f32_e32 v0, 0.15915494, v0
; GFX8-NEXT: v_fract_f32_e32 v0, v0
; GFX8-NEXT: v_sin_f32_e32 v0, v0
; GFX8-NEXT: v_cvt_f16_f32_e32 v2, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: flat_store_short v[0:1], v2
; GFX8-NEXT: s_endpgm
;
; GFX9-LABEL: sin_f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: global_load_ushort v0, v[0:1], off
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v0, 0.15915494, v0
; GFX9-NEXT: v_sin_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v0
; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: global_store_short v[0:1], v2, off
; GFX9-NEXT: s_endpgm
%a.val = load half, half addrspace(1)* %a %a.val = load half, half addrspace(1)* %a
%r.val = call half @llvm.sin.f16(half %a.val) %r.val = call half @llvm.sin.f16(half %a.val)
store half %r.val, half addrspace(1)* %r store half %r.val, half addrspace(1)* %r
ret void ret void
} }
; GCN-LABEL: {{^}}sin_v2f16: define amdgpu_kernel void @sin_v2f16(<2 x half> addrspace(1)* %r, <2 x half> addrspace(1)* %a) {
; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]] ; GFX6-LABEL: sin_v2f16:
; SI: s_mov_b32 [[HALF_PI:s[0-9]+]], 0x3e22f983{{$}} ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]] ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] ; GFX6-NEXT: s_mov_b32 s2, -1
; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]] ; GFX6-NEXT: s_mov_b32 s10, s2
; SI: v_mul_f32_e32 v[[M_F32_0:[0-9]+]], [[HALF_PI]], v[[A_F32_0]] ; GFX6-NEXT: s_mov_b32 s11, s3
; SI: v_fract_f32_e32 v[[F_F32_0:[0-9]+]], v[[M_F32_0]] ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; SI: v_mul_f32_e32 v[[M_F32_1:[0-9]+]], [[HALF_PI]], v[[A_F32_1]] ; GFX6-NEXT: s_mov_b32 s8, s6
; SI: v_fract_f32_e32 v[[F_F32_1:[0-9]+]], v[[M_F32_1]] ; GFX6-NEXT: s_mov_b32 s9, s7
; SI: v_sin_f32_e32 v[[R_F32_1:[0-9]+]], v[[F_F32_1]] ; GFX6-NEXT: buffer_load_dword v0, off, s[8:11], 0
; SI: v_sin_f32_e32 v[[R_F32_0:[0-9]+]], v[[F_F32_0]] ; GFX6-NEXT: s_mov_b32 s0, 0x3e22f983
; SI: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]] ; GFX6-NEXT: s_mov_b32 s1, s5
; GFX6-NEXT: s_waitcnt vmcnt(0)
; VIGFX9-DAG: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]] ; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v0
; VIGFX9-DAG: v_cvt_f32_f16_sdwa v[[A_F32_1:[0-9]+]], v[[A_V2_F16]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; VIGFX9-DAG: v_mul_f32_e32 v[[M_F32_0:[0-9]+]], 0.15915494, v[[A_F32_0]] ; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
; VIGFX9-DAG: v_mul_f32_e32 v[[M_F32_1:[0-9]+]], 0.15915494, v[[A_F32_1]] ; GFX6-NEXT: v_mul_f32_e32 v1, s0, v1
; VI-DAG: v_fract_f32_e32 v[[F_F32_0:[0-9]+]], v[[M_F32_0]] ; GFX6-NEXT: v_fract_f32_e32 v1, v1
; VI-DAG: v_fract_f32_e32 v[[F_F32_1:[0-9]+]], v[[M_F32_1]] ; GFX6-NEXT: v_mul_f32_e32 v0, s0, v0
; VI-DAG: v_sin_f32_e32 v[[R_F32_1:[0-9]+]], v[[F_F32_1]] ; GFX6-NEXT: v_fract_f32_e32 v0, v0
; VI-DAG: v_sin_f32_e32 v[[R_F32_0:[0-9]+]], v[[F_F32_0]] ; GFX6-NEXT: v_sin_f32_e32 v0, v0
; GFX9-DAG: v_sin_f32_e32 v[[R_F32_1:[0-9]+]], v[[M_F32_1]] ; GFX6-NEXT: v_sin_f32_e32 v1, v1
; GFX9-DAG: v_sin_f32_e32 v[[R_F32_0:[0-9]+]], v[[M_F32_0]] ; GFX6-NEXT: s_mov_b32 s0, s4
; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
; GCN-DAG: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]] ; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] ; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]] ; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
; VI-DAG: v_cvt_f16_f32_sdwa v[[R_F16_1:[0-9]+]], v[[R_F32_1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD ;
; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_1]] ; GFX8-LABEL: sin_v2f16:
; GFX8: ; %bb.0:
; GFX9-DAG: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]] ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-DAG: v_and_b32_e32 v[[R2_F16_0:[0-9]+]], 0xffff, v[[R_F16_0]] ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DAG: v_lshl_or_b32 v[[R_V2_F16:[0-9]+]], v[[R_F16_1]], 16, v[[R2_F16_0]] ; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GCN: buffer_store_dword v[[R_V2_F16]] ; GFX8-NEXT: flat_load_dword v0, v[0:1]
; GCN: s_endpgm ; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
define amdgpu_kernel void @sin_v2f16( ; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
<2 x half> addrspace(1)* %r, ; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0
<2 x half> addrspace(1)* %a) { ; GFX8-NEXT: v_mul_f32_e32 v1, 0.15915494, v1
entry: ; GFX8-NEXT: v_mul_f32_e32 v0, 0.15915494, v0
; GFX8-NEXT: v_fract_f32_e32 v1, v1
; GFX8-NEXT: v_fract_f32_e32 v0, v0
; GFX8-NEXT: v_sin_f32_e32 v1, v1
; GFX8-NEXT: v_sin_f32_e32 v0, v0
; GFX8-NEXT: v_cvt_f16_f32_sdwa v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
; GFX8-NEXT: v_cvt_f16_f32_e32 v3, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_or_b32_e32 v2, v3, v2
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
;
; GFX9-LABEL: sin_v2f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: global_load_dword v0, v[0:1], off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v0
; GFX9-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-NEXT: v_mul_f32_e32 v1, 0.15915494, v1
; GFX9-NEXT: v_mul_f32_e32 v0, 0.15915494, v0
; GFX9-NEXT: v_sin_f32_e32 v1, v1
; GFX9-NEXT: v_sin_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v1
; GFX9-NEXT: v_cvt_f16_f32_e32 v3, v0
; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_endpgm
%a.val = load <2 x half>, <2 x half> addrspace(1)* %a %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
%r.val = call <2 x half> @llvm.sin.v2f16(<2 x half> %a.val) %r.val = call <2 x half> @llvm.sin.v2f16(<2 x half> %a.val)
store <2 x half> %r.val, <2 x half> addrspace(1)* %r store <2 x half> %r.val, <2 x half> addrspace(1)* %r
ret void ret void
} }
declare half @llvm.sin.f16(half %a)
declare <2 x half> @llvm.sin.v2f16(<2 x half> %a)