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[InstCombine] visitAnd - add some ((val OP C1) & C2) vector test coverage

This commit is contained in:
Simon Pilgrim 2020-10-16 15:05:54 +01:00
parent 253f24cf4c
commit fe8281e2d0
2 changed files with 72 additions and 0 deletions
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33
llvm/test/Transforms/InstCombine/add.ll
View File

@ -348,6 +348,39 @@ define i8 @test16(i8 %A) {
ret i8 %C
}
define <2 x i8> @test16_uniform(<2 x i8> %A) {
; CHECK-LABEL: @test16_uniform(
; CHECK-NEXT: [[B:%.*]] = add <2 x i8> [[A:%.*]], <i8 16, i8 16>
; CHECK-NEXT: [[C:%.*]] = and <2 x i8> [[B]], <i8 16, i8 16>
; CHECK-NEXT: ret <2 x i8> [[C]]
;
%B = add <2 x i8> %A, <i8 16, i8 16>
%C = and <2 x i8> %B, <i8 16, i8 16>
ret <2 x i8> %C
}
define <2 x i8> @test16_undef(<2 x i8> %A) {
; CHECK-LABEL: @test16_undef(
; CHECK-NEXT: [[B:%.*]] = add <2 x i8> [[A:%.*]], <i8 16, i8 undef>
; CHECK-NEXT: [[C:%.*]] = and <2 x i8> [[B]], <i8 16, i8 undef>
; CHECK-NEXT: ret <2 x i8> [[C]]
;
%B = add <2 x i8> %A, <i8 16, i8 undef>
%C = and <2 x i8> %B, <i8 16, i8 undef>
ret <2 x i8> %C
}
define <2 x i8> @test16_nonuniform(<2 x i8> %A) {
; CHECK-LABEL: @test16_nonuniform(
; CHECK-NEXT: [[B:%.*]] = add <2 x i8> [[A:%.*]], <i8 16, i8 4>
; CHECK-NEXT: [[C:%.*]] = and <2 x i8> [[B]], <i8 16, i8 4>
; CHECK-NEXT: ret <2 x i8> [[C]]
;
%B = add <2 x i8> %A, <i8 16, i8 4>
%C = and <2 x i8> %B, <i8 16, i8 4>
ret <2 x i8> %C
}
define i32 @test17(i32 %A) {
; CHECK-LABEL: @test17(
; CHECK-NEXT: [[C:%.*]] = sub i32 0, [[A:%.*]]

39
llvm/test/Transforms/InstCombine/and.ll
View File

@ -479,6 +479,19 @@ define i64 @test35(i32 %X) {
ret i64 %res
}
define <2 x i64> @test35_uniform(<2 x i32> %X) {
; CHECK-LABEL: @test35_uniform(
; CHECK-NEXT: [[ZEXT:%.*]] = zext <2 x i32> [[X:%.*]] to <2 x i64>
; CHECK-NEXT: [[ZSUB:%.*]] = sub nsw <2 x i64> zeroinitializer, [[ZEXT]]
; CHECK-NEXT: [[RES:%.*]] = and <2 x i64> [[ZSUB]], <i64 240, i64 240>
; CHECK-NEXT: ret <2 x i64> [[RES]]
;
%zext = zext <2 x i32> %X to <2 x i64>
%zsub = sub <2 x i64> zeroinitializer, %zext
%res = and <2 x i64> %zsub, <i64 240, i64 240>
ret <2 x i64> %res
}
define i64 @test36(i32 %X) {
; CHECK-LABEL: @test36(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], 7
@ -492,6 +505,19 @@ define i64 @test36(i32 %X) {
ret i64 %res
}
define <2 x i64> @test36_undef(<2 x i32> %X) {
; CHECK-LABEL: @test36_undef(
; CHECK-NEXT: [[ZEXT:%.*]] = zext <2 x i32> [[X:%.*]] to <2 x i64>
; CHECK-NEXT: [[ZSUB:%.*]] = add <2 x i64> [[ZEXT]], <i64 7, i64 undef>
; CHECK-NEXT: [[RES:%.*]] = and <2 x i64> [[ZSUB]], <i64 240, i64 undef>
; CHECK-NEXT: ret <2 x i64> [[RES]]
;
%zext = zext <2 x i32> %X to <2 x i64>
%zsub = add <2 x i64> %zext, <i64 7, i64 undef>
%res = and <2 x i64> %zsub, <i64 240, i64 undef>
ret <2 x i64> %res
}
define i64 @test37(i32 %X) {
; CHECK-LABEL: @test37(
; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[X:%.*]], 7
@ -505,6 +531,19 @@ define i64 @test37(i32 %X) {
ret i64 %res
}
define <2 x i64> @test37_nonuniform(<2 x i32> %X) {
; CHECK-LABEL: @test37_nonuniform(
; CHECK-NEXT: [[ZEXT:%.*]] = zext <2 x i32> [[X:%.*]] to <2 x i64>
; CHECK-NEXT: [[ZSUB:%.*]] = mul nuw nsw <2 x i64> [[ZEXT]], <i64 7, i64 9>
; CHECK-NEXT: [[RES:%.*]] = and <2 x i64> [[ZSUB]], <i64 240, i64 110>
; CHECK-NEXT: ret <2 x i64> [[RES]]
;
%zext = zext <2 x i32> %X to <2 x i64>
%zsub = mul <2 x i64> %zext, <i64 7, i64 9>
%res = and <2 x i64> %zsub, <i64 240, i64 110>
ret <2 x i64> %res
}
define i64 @test38(i32 %X) {
; CHECK-LABEL: @test38(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 240