From fe3bbb251b52b79243c69365127fa919f1ec1584 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 27 Nov 2018 02:57:23 +0000 Subject: [PATCH] [X86] Add a bunch of test cases for storing a scalar bitcasted from a vXi1 type. Currently a store combine will absorb the bitcast before our combine that turns bitcasts into movmsk gets a chance to run. This results in a store being created with a vXi1 type. Type legalization then promotes the input type and makes this a truncating store. Then we badly scalarize this store. Currently we avoid this on v8i1->i8 bitcasts due to an incompletely qualified(per the original intention) check in isLoadBitCastBeneficial. An easy fix is to disable this for all vXi1->iX bitcasts on pre-avx512 targets. We'll still generate terrible code if the IR explicitly contains a store of vXi1 without a bitcast. We could probably solve that by just turning all stores of vXi1 into (store (iX (bitcast))) as an early DAG combine. llvm-svn: 347631 --- llvm/test/CodeGen/X86/bitcast-setcc-128.ll | 319 ++++ llvm/test/CodeGen/X86/bitcast-setcc-256.ll | 803 +++++++++++ llvm/test/CodeGen/X86/bitcast-setcc-512.ll | 1518 ++++++++++++++++++++ 3 files changed, 2640 insertions(+) diff --git a/llvm/test/CodeGen/X86/bitcast-setcc-128.ll b/llvm/test/CodeGen/X86/bitcast-setcc-128.ll index 3f78d0c9c5cc..618b2093bdd6 100644 --- a/llvm/test/CodeGen/X86/bitcast-setcc-128.ll +++ b/llvm/test/CodeGen/X86/bitcast-setcc-128.ll @@ -741,3 +741,322 @@ entry: %e = bitcast <64 x i1> %d to i64 ret i64 %e } + +define void @bitcast_16i8_store(i16* %p, <16 x i8> %a0) { +; SSE2-SSSE3-LABEL: bitcast_16i8_store: +; SSE2-SSSE3: # %bb.0: +; SSE2-SSSE3-NEXT: pxor %xmm1, %xmm1 +; SSE2-SSSE3-NEXT: pcmpgtb %xmm0, %xmm1 +; SSE2-SSSE3-NEXT: movdqa %xmm1, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: leal (%rcx,%rax,2), %eax +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: leal (%rax,%rcx,4), %eax +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: leal (%rax,%rcx,8), %eax +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: shll $4, %ecx +; SSE2-SSSE3-NEXT: orl %eax, %ecx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: shll $5, %eax +; SSE2-SSSE3-NEXT: orl %ecx, %eax +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: shll $6, %ecx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx +; SSE2-SSSE3-NEXT: andl $1, %edx +; SSE2-SSSE3-NEXT: shll $7, %edx +; SSE2-SSSE3-NEXT: orl %ecx, %edx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: shll $8, %ecx +; SSE2-SSSE3-NEXT: orl %edx, %ecx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx +; SSE2-SSSE3-NEXT: andl $1, %edx +; SSE2-SSSE3-NEXT: shll $9, %edx +; SSE2-SSSE3-NEXT: orl %ecx, %edx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: shll $10, %ecx +; SSE2-SSSE3-NEXT: orl %edx, %ecx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx +; SSE2-SSSE3-NEXT: andl $1, %edx +; SSE2-SSSE3-NEXT: shll $11, %edx +; SSE2-SSSE3-NEXT: orl %ecx, %edx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: shll $12, %ecx +; SSE2-SSSE3-NEXT: orl %edx, %ecx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx +; SSE2-SSSE3-NEXT: andl $1, %edx +; SSE2-SSSE3-NEXT: shll $13, %edx +; SSE2-SSSE3-NEXT: orl %ecx, %edx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: shll $14, %ecx +; SSE2-SSSE3-NEXT: orl %edx, %ecx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx +; SSE2-SSSE3-NEXT: shll $15, %edx +; SSE2-SSSE3-NEXT: orl %ecx, %edx +; SSE2-SSSE3-NEXT: orl %eax, %edx +; SSE2-SSSE3-NEXT: movw %dx, (%rdi) +; SSE2-SSSE3-NEXT: retq +; +; AVX12-LABEL: bitcast_16i8_store: +; AVX12: # %bb.0: +; AVX12-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX12-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0 +; AVX12-NEXT: vpextrb $1, %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: vpextrb $0, %xmm0, %ecx +; AVX12-NEXT: andl $1, %ecx +; AVX12-NEXT: leal (%rcx,%rax,2), %eax +; AVX12-NEXT: vpextrb $2, %xmm0, %ecx +; AVX12-NEXT: andl $1, %ecx +; AVX12-NEXT: leal (%rax,%rcx,4), %eax +; AVX12-NEXT: vpextrb $3, %xmm0, %ecx +; AVX12-NEXT: andl $1, %ecx +; AVX12-NEXT: leal (%rax,%rcx,8), %eax +; AVX12-NEXT: vpextrb $4, %xmm0, %ecx +; AVX12-NEXT: andl $1, %ecx +; AVX12-NEXT: shll $4, %ecx +; AVX12-NEXT: orl %eax, %ecx +; AVX12-NEXT: vpextrb $5, %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: shll $5, %eax +; AVX12-NEXT: orl %ecx, %eax +; AVX12-NEXT: vpextrb $6, %xmm0, %ecx +; AVX12-NEXT: andl $1, %ecx +; AVX12-NEXT: shll $6, %ecx +; AVX12-NEXT: vpextrb $7, %xmm0, %edx +; AVX12-NEXT: andl $1, %edx +; AVX12-NEXT: shll $7, %edx +; AVX12-NEXT: orl %ecx, %edx +; AVX12-NEXT: vpextrb $8, %xmm0, %ecx +; AVX12-NEXT: andl $1, %ecx +; AVX12-NEXT: shll $8, %ecx +; AVX12-NEXT: orl %edx, %ecx +; AVX12-NEXT: vpextrb $9, %xmm0, %edx +; AVX12-NEXT: andl $1, %edx +; AVX12-NEXT: shll $9, %edx +; AVX12-NEXT: orl %ecx, %edx +; AVX12-NEXT: vpextrb $10, %xmm0, %ecx +; AVX12-NEXT: andl $1, %ecx +; AVX12-NEXT: shll $10, %ecx +; AVX12-NEXT: orl %edx, %ecx +; AVX12-NEXT: vpextrb $11, %xmm0, %edx +; AVX12-NEXT: andl $1, %edx +; AVX12-NEXT: shll $11, %edx +; AVX12-NEXT: orl %ecx, %edx +; AVX12-NEXT: vpextrb $12, %xmm0, %ecx +; AVX12-NEXT: andl $1, %ecx +; AVX12-NEXT: shll $12, %ecx +; AVX12-NEXT: orl %edx, %ecx +; AVX12-NEXT: vpextrb $13, %xmm0, %edx +; AVX12-NEXT: andl $1, %edx +; AVX12-NEXT: shll $13, %edx +; AVX12-NEXT: orl %ecx, %edx +; AVX12-NEXT: vpextrb $14, %xmm0, %ecx +; AVX12-NEXT: andl $1, %ecx +; AVX12-NEXT: shll $14, %ecx +; AVX12-NEXT: orl %edx, %ecx +; AVX12-NEXT: vpextrb $15, %xmm0, %edx +; AVX12-NEXT: shll $15, %edx +; AVX12-NEXT: orl %ecx, %edx +; AVX12-NEXT: orl %eax, %edx +; AVX12-NEXT: movw %dx, (%rdi) +; AVX12-NEXT: retq +; +; AVX512F-LABEL: bitcast_16i8_store: +; AVX512F: # %bb.0: +; AVX512F-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512F-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0 +; AVX512F-NEXT: vpmovsxbd %xmm0, %zmm0 +; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k0 +; AVX512F-NEXT: kmovw %k0, (%rdi) +; AVX512F-NEXT: vzeroupper +; AVX512F-NEXT: retq +; +; AVX512BW-LABEL: bitcast_16i8_store: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: vpmovb2m %xmm0, %k0 +; AVX512BW-NEXT: kmovw %k0, (%rdi) +; AVX512BW-NEXT: retq + %a1 = icmp slt <16 x i8> %a0, zeroinitializer + %a2 = bitcast <16 x i1> %a1 to i16 + store i16 %a2, i16* %p + ret void +} + +define void @bitcast_8i16_store(i8* %p, <8 x i16> %a0) { +; SSE2-SSSE3-LABEL: bitcast_8i16_store: +; SSE2-SSSE3: # %bb.0: +; SSE2-SSSE3-NEXT: pxor %xmm1, %xmm1 +; SSE2-SSSE3-NEXT: pcmpgtw %xmm0, %xmm1 +; SSE2-SSSE3-NEXT: packsswb %xmm0, %xmm1 +; SSE2-SSSE3-NEXT: pmovmskb %xmm1, %eax +; SSE2-SSSE3-NEXT: movb %al, (%rdi) +; SSE2-SSSE3-NEXT: retq +; +; AVX12-LABEL: bitcast_8i16_store: +; AVX12: # %bb.0: +; AVX12-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX12-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0 +; AVX12-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 +; AVX12-NEXT: vpmovmskb %xmm0, %eax +; AVX12-NEXT: movb %al, (%rdi) +; AVX12-NEXT: retq +; +; AVX512F-LABEL: bitcast_8i16_store: +; AVX512F: # %bb.0: +; AVX512F-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512F-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0 +; AVX512F-NEXT: vpmovsxwd %xmm0, %ymm0 +; AVX512F-NEXT: vptestmd %ymm0, %ymm0, %k0 +; AVX512F-NEXT: kmovw %k0, %eax +; AVX512F-NEXT: movb %al, (%rdi) +; AVX512F-NEXT: vzeroupper +; AVX512F-NEXT: retq +; +; AVX512BW-LABEL: bitcast_8i16_store: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: vpmovw2m %xmm0, %k0 +; AVX512BW-NEXT: kmovd %k0, %eax +; AVX512BW-NEXT: movb %al, (%rdi) +; AVX512BW-NEXT: retq + %a1 = icmp slt <8 x i16> %a0, zeroinitializer + %a2 = bitcast <8 x i1> %a1 to i8 + store i8 %a2, i8* %p + ret void +} + +define void @bitcast_4i32_store(i4* %p, <4 x i32> %a0) { +; SSE2-SSSE3-LABEL: bitcast_4i32_store: +; SSE2-SSSE3: # %bb.0: +; SSE2-SSSE3-NEXT: pxor %xmm1, %xmm1 +; SSE2-SSSE3-NEXT: pcmpgtd %xmm0, %xmm1 +; SSE2-SSSE3-NEXT: movd %xmm1, %eax +; SSE2-SSSE3-NEXT: andb $1, %al +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,2,3] +; SSE2-SSSE3-NEXT: movd %xmm0, %ecx +; SSE2-SSSE3-NEXT: andb $1, %cl +; SSE2-SSSE3-NEXT: addb %cl, %cl +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,0,1] +; SSE2-SSSE3-NEXT: movd %xmm0, %edx +; SSE2-SSSE3-NEXT: andb $1, %dl +; SSE2-SSSE3-NEXT: shlb $2, %dl +; SSE2-SSSE3-NEXT: orb %cl, %dl +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm1[3,1,2,3] +; SSE2-SSSE3-NEXT: movd %xmm0, %ecx +; SSE2-SSSE3-NEXT: shlb $3, %cl +; SSE2-SSSE3-NEXT: orb %dl, %cl +; SSE2-SSSE3-NEXT: orb %al, %cl +; SSE2-SSSE3-NEXT: andb $15, %cl +; SSE2-SSSE3-NEXT: movb %cl, (%rdi) +; SSE2-SSSE3-NEXT: retq +; +; AVX12-LABEL: bitcast_4i32_store: +; AVX12: # %bb.0: +; AVX12-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX12-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 +; AVX12-NEXT: vmovd %xmm0, %eax +; AVX12-NEXT: andb $1, %al +; AVX12-NEXT: vpextrd $1, %xmm0, %ecx +; AVX12-NEXT: andb $1, %cl +; AVX12-NEXT: addb %cl, %cl +; AVX12-NEXT: vpextrd $2, %xmm0, %edx +; AVX12-NEXT: andb $1, %dl +; AVX12-NEXT: shlb $2, %dl +; AVX12-NEXT: orb %cl, %dl +; AVX12-NEXT: vpextrd $3, %xmm0, %ecx +; AVX12-NEXT: shlb $3, %cl +; AVX12-NEXT: orb %dl, %cl +; AVX12-NEXT: orb %al, %cl +; AVX12-NEXT: andb $15, %cl +; AVX12-NEXT: movb %cl, (%rdi) +; AVX12-NEXT: retq +; +; AVX512F-LABEL: bitcast_4i32_store: +; AVX512F: # %bb.0: +; AVX512F-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512F-NEXT: vpcmpgtd %xmm0, %xmm1, %k0 +; AVX512F-NEXT: kmovw %k0, %eax +; AVX512F-NEXT: movb %al, (%rdi) +; AVX512F-NEXT: retq +; +; AVX512BW-LABEL: bitcast_4i32_store: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512BW-NEXT: vpcmpgtd %xmm0, %xmm1, %k0 +; AVX512BW-NEXT: kmovd %k0, %eax +; AVX512BW-NEXT: movb %al, (%rdi) +; AVX512BW-NEXT: retq + %a1 = icmp slt <4 x i32> %a0, zeroinitializer + %a2 = bitcast <4 x i1> %a1 to i4 + store i4 %a2, i4* %p + ret void +} + +define void @bitcast_2i64_store(i2* %p, <2 x i64> %a0) { +; SSE2-SSSE3-LABEL: bitcast_2i64_store: +; SSE2-SSSE3: # %bb.0: +; SSE2-SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648] +; SSE2-SSSE3-NEXT: pxor %xmm1, %xmm0 +; SSE2-SSSE3-NEXT: movdqa %xmm1, %xmm2 +; SSE2-SSSE3-NEXT: pcmpgtd %xmm0, %xmm2 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2] +; SSE2-SSSE3-NEXT: pcmpeqd %xmm1, %xmm0 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] +; SSE2-SSSE3-NEXT: pand %xmm3, %xmm0 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] +; SSE2-SSSE3-NEXT: por %xmm0, %xmm1 +; SSE2-SSSE3-NEXT: movq %xmm1, %rax +; SSE2-SSSE3-NEXT: andb $1, %al +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,0,1] +; SSE2-SSSE3-NEXT: movq %xmm0, %rcx +; SSE2-SSSE3-NEXT: addb %cl, %cl +; SSE2-SSSE3-NEXT: orb %al, %cl +; SSE2-SSSE3-NEXT: andb $3, %cl +; SSE2-SSSE3-NEXT: movb %cl, (%rdi) +; SSE2-SSSE3-NEXT: retq +; +; AVX12-LABEL: bitcast_2i64_store: +; AVX12: # %bb.0: +; AVX12-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX12-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 +; AVX12-NEXT: vpextrq $1, %xmm0, %rax +; AVX12-NEXT: addb %al, %al +; AVX12-NEXT: vmovq %xmm0, %rcx +; AVX12-NEXT: andb $1, %cl +; AVX12-NEXT: orb %al, %cl +; AVX12-NEXT: andb $3, %cl +; AVX12-NEXT: movb %cl, (%rdi) +; AVX12-NEXT: retq +; +; AVX512F-LABEL: bitcast_2i64_store: +; AVX512F: # %bb.0: +; AVX512F-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512F-NEXT: vpcmpgtq %xmm0, %xmm1, %k0 +; AVX512F-NEXT: kmovw %k0, %eax +; AVX512F-NEXT: movb %al, (%rdi) +; AVX512F-NEXT: retq +; +; AVX512BW-LABEL: bitcast_2i64_store: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512BW-NEXT: vpcmpgtq %xmm0, %xmm1, %k0 +; AVX512BW-NEXT: kmovd %k0, %eax +; AVX512BW-NEXT: movb %al, (%rdi) +; AVX512BW-NEXT: retq + %a1 = icmp slt <2 x i64> %a0, zeroinitializer + %a2 = bitcast <2 x i1> %a1 to i2 + store i2 %a2, i2* %p + ret void +} diff --git a/llvm/test/CodeGen/X86/bitcast-setcc-256.ll b/llvm/test/CodeGen/X86/bitcast-setcc-256.ll index 5f468f3b0d1f..149a710f9993 100644 --- a/llvm/test/CodeGen/X86/bitcast-setcc-256.ll +++ b/llvm/test/CodeGen/X86/bitcast-setcc-256.ll @@ -313,3 +313,806 @@ define i4 @v4f64(<4 x double> %a, <4 x double> %b) { %res = bitcast <4 x i1> %x to i4 ret i4 %res } + +define void @bitcast_32i8_store(i32* %p, <32 x i8> %a0) { +; SSE2-SSSE3-LABEL: bitcast_32i8_store: +; SSE2-SSSE3: # %bb.0: +; SSE2-SSSE3-NEXT: pxor %xmm3, %xmm3 +; SSE2-SSSE3-NEXT: pxor %xmm2, %xmm2 +; SSE2-SSSE3-NEXT: pcmpgtb %xmm0, %xmm2 +; SSE2-SSSE3-NEXT: pcmpgtb %xmm1, %xmm3 +; SSE2-SSSE3-NEXT: movdqa %xmm3, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: leal (%rcx,%rax,2), %eax +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: leal (%rax,%rcx,4), %eax +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: leal (%rax,%rcx,8), %eax +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: shll $4, %ecx +; SSE2-SSSE3-NEXT: orl %eax, %ecx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: shll $5, %eax +; SSE2-SSSE3-NEXT: orl %ecx, %eax +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: shll $6, %ecx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx +; SSE2-SSSE3-NEXT: andl $1, %edx +; SSE2-SSSE3-NEXT: shll $7, %edx +; SSE2-SSSE3-NEXT: orl %ecx, %edx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: shll $8, %ecx +; SSE2-SSSE3-NEXT: orl %edx, %ecx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx +; SSE2-SSSE3-NEXT: andl $1, %edx +; SSE2-SSSE3-NEXT: shll $9, %edx +; SSE2-SSSE3-NEXT: orl %ecx, %edx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: shll $10, %ecx +; SSE2-SSSE3-NEXT: orl %edx, %ecx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx +; SSE2-SSSE3-NEXT: andl $1, %edx +; SSE2-SSSE3-NEXT: shll $11, %edx +; SSE2-SSSE3-NEXT: orl %ecx, %edx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: shll $12, %ecx +; SSE2-SSSE3-NEXT: orl %edx, %ecx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx +; SSE2-SSSE3-NEXT: andl $1, %edx +; SSE2-SSSE3-NEXT: shll $13, %edx +; SSE2-SSSE3-NEXT: orl %ecx, %edx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: shll $14, %ecx +; SSE2-SSSE3-NEXT: orl %edx, %ecx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx +; SSE2-SSSE3-NEXT: shll $15, %edx +; SSE2-SSSE3-NEXT: orl %ecx, %edx +; SSE2-SSSE3-NEXT: orl %eax, %edx +; SSE2-SSSE3-NEXT: movw %dx, 2(%rdi) +; SSE2-SSSE3-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: leal (%rcx,%rax,2), %eax +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: leal (%rax,%rcx,4), %eax +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: leal (%rax,%rcx,8), %eax +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: shll $4, %ecx +; SSE2-SSSE3-NEXT: orl %eax, %ecx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: shll $5, %eax +; SSE2-SSSE3-NEXT: orl %ecx, %eax +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: shll $6, %ecx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx +; SSE2-SSSE3-NEXT: andl $1, %edx +; SSE2-SSSE3-NEXT: shll $7, %edx +; SSE2-SSSE3-NEXT: orl %ecx, %edx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: shll $8, %ecx +; SSE2-SSSE3-NEXT: orl %edx, %ecx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx +; SSE2-SSSE3-NEXT: andl $1, %edx +; SSE2-SSSE3-NEXT: shll $9, %edx +; SSE2-SSSE3-NEXT: orl %ecx, %edx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: shll $10, %ecx +; SSE2-SSSE3-NEXT: orl %edx, %ecx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx +; SSE2-SSSE3-NEXT: andl $1, %edx +; SSE2-SSSE3-NEXT: shll $11, %edx +; SSE2-SSSE3-NEXT: orl %ecx, %edx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: shll $12, %ecx +; SSE2-SSSE3-NEXT: orl %edx, %ecx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx +; SSE2-SSSE3-NEXT: andl $1, %edx +; SSE2-SSSE3-NEXT: shll $13, %edx +; SSE2-SSSE3-NEXT: orl %ecx, %edx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: shll $14, %ecx +; SSE2-SSSE3-NEXT: orl %edx, %ecx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx +; SSE2-SSSE3-NEXT: shll $15, %edx +; SSE2-SSSE3-NEXT: orl %ecx, %edx +; SSE2-SSSE3-NEXT: orl %eax, %edx +; SSE2-SSSE3-NEXT: movw %dx, (%rdi) +; SSE2-SSSE3-NEXT: retq +; +; AVX1-LABEL: bitcast_32i8_store: +; AVX1: # %bb.0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vpcmpgtb %xmm1, %xmm2, %xmm1 +; AVX1-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm0 +; AVX1-NEXT: vpextrb $1, %xmm0, %eax +; AVX1-NEXT: andl $1, %eax +; AVX1-NEXT: vpextrb $0, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: leal (%rcx,%rax,2), %eax +; AVX1-NEXT: vpextrb $2, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: leal (%rax,%rcx,4), %eax +; AVX1-NEXT: vpextrb $3, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: leal (%rax,%rcx,8), %eax +; AVX1-NEXT: vpextrb $4, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $4, %ecx +; AVX1-NEXT: orl %eax, %ecx +; AVX1-NEXT: vpextrb $5, %xmm0, %eax +; AVX1-NEXT: andl $1, %eax +; AVX1-NEXT: shll $5, %eax +; AVX1-NEXT: orl %ecx, %eax +; AVX1-NEXT: vpextrb $6, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $6, %ecx +; AVX1-NEXT: vpextrb $7, %xmm0, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $7, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $8, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $8, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $9, %xmm0, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $9, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $10, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $10, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $11, %xmm0, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $11, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $12, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $12, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $13, %xmm0, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $13, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $14, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $14, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $15, %xmm0, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $15, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $0, %xmm1, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $16, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $1, %xmm1, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $17, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $2, %xmm1, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $18, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $3, %xmm1, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $19, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $4, %xmm1, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $20, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $5, %xmm1, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $21, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $6, %xmm1, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $22, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $7, %xmm1, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $23, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $8, %xmm1, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $24, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $9, %xmm1, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $25, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $10, %xmm1, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $26, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $11, %xmm1, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $27, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $12, %xmm1, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $28, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $13, %xmm1, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $29, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $14, %xmm1, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $30, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $15, %xmm1, %edx +; AVX1-NEXT: shll $31, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: orl %eax, %edx +; AVX1-NEXT: movl %edx, (%rdi) +; AVX1-NEXT: vzeroupper +; AVX1-NEXT: retq +; +; AVX2-LABEL: bitcast_32i8_store: +; AVX2: # %bb.0: +; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX2-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm0 +; AVX2-NEXT: vpextrb $1, %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: vpextrb $0, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: leal (%rcx,%rax,2), %eax +; AVX2-NEXT: vpextrb $2, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: leal (%rax,%rcx,4), %eax +; AVX2-NEXT: vpextrb $3, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: leal (%rax,%rcx,8), %eax +; AVX2-NEXT: vpextrb $4, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $4, %ecx +; AVX2-NEXT: orl %eax, %ecx +; AVX2-NEXT: vpextrb $5, %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: shll $5, %eax +; AVX2-NEXT: orl %ecx, %eax +; AVX2-NEXT: vpextrb $6, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $6, %ecx +; AVX2-NEXT: vpextrb $7, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $7, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $8, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $8, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $9, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $9, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $10, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $10, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $11, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $11, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $12, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $12, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $13, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $13, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $14, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $14, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $15, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $15, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 +; AVX2-NEXT: vpextrb $0, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $16, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $1, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $17, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $2, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $18, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $3, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $19, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $4, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $20, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $5, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $21, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $6, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $22, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $7, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $23, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $8, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $24, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $9, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $25, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $10, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $26, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $11, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $27, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $12, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $28, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $13, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $29, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $14, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $30, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $15, %xmm0, %edx +; AVX2-NEXT: shll $31, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: orl %eax, %edx +; AVX2-NEXT: movl %edx, (%rdi) +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq +; +; AVX512F-LABEL: bitcast_32i8_store: +; AVX512F: # %bb.0: +; AVX512F-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512F-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm0 +; AVX512F-NEXT: vpmovsxbd %xmm0, %zmm1 +; AVX512F-NEXT: vptestmd %zmm1, %zmm1, %k0 +; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0 +; AVX512F-NEXT: vpmovsxbd %xmm0, %zmm0 +; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k1 +; AVX512F-NEXT: kmovw %k1, 2(%rdi) +; AVX512F-NEXT: kmovw %k0, (%rdi) +; AVX512F-NEXT: vzeroupper +; AVX512F-NEXT: retq +; +; AVX512BW-LABEL: bitcast_32i8_store: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: vpmovb2m %ymm0, %k0 +; AVX512BW-NEXT: kmovd %k0, (%rdi) +; AVX512BW-NEXT: vzeroupper +; AVX512BW-NEXT: retq + %a1 = icmp slt <32 x i8> %a0, zeroinitializer + %a2 = bitcast <32 x i1> %a1 to i32 + store i32 %a2, i32* %p + ret void +} + +define void @bitcast_16i16_store(i16* %p, <16 x i16> %a0) { +; SSE2-SSSE3-LABEL: bitcast_16i16_store: +; SSE2-SSSE3: # %bb.0: +; SSE2-SSSE3-NEXT: pxor %xmm2, %xmm2 +; SSE2-SSSE3-NEXT: pxor %xmm3, %xmm3 +; SSE2-SSSE3-NEXT: pcmpgtw %xmm1, %xmm3 +; SSE2-SSSE3-NEXT: pcmpgtw %xmm0, %xmm2 +; SSE2-SSSE3-NEXT: packsswb %xmm3, %xmm2 +; SSE2-SSSE3-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: leal (%rcx,%rax,2), %eax +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: leal (%rax,%rcx,4), %eax +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: leal (%rax,%rcx,8), %eax +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: shll $4, %ecx +; SSE2-SSSE3-NEXT: orl %eax, %ecx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: shll $5, %eax +; SSE2-SSSE3-NEXT: orl %ecx, %eax +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: shll $6, %ecx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx +; SSE2-SSSE3-NEXT: andl $1, %edx +; SSE2-SSSE3-NEXT: shll $7, %edx +; SSE2-SSSE3-NEXT: orl %ecx, %edx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: shll $8, %ecx +; SSE2-SSSE3-NEXT: orl %edx, %ecx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx +; SSE2-SSSE3-NEXT: andl $1, %edx +; SSE2-SSSE3-NEXT: shll $9, %edx +; SSE2-SSSE3-NEXT: orl %ecx, %edx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: shll $10, %ecx +; SSE2-SSSE3-NEXT: orl %edx, %ecx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx +; SSE2-SSSE3-NEXT: andl $1, %edx +; SSE2-SSSE3-NEXT: shll $11, %edx +; SSE2-SSSE3-NEXT: orl %ecx, %edx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: shll $12, %ecx +; SSE2-SSSE3-NEXT: orl %edx, %ecx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx +; SSE2-SSSE3-NEXT: andl $1, %edx +; SSE2-SSSE3-NEXT: shll $13, %edx +; SSE2-SSSE3-NEXT: orl %ecx, %edx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx +; SSE2-SSSE3-NEXT: andl $1, %ecx +; SSE2-SSSE3-NEXT: shll $14, %ecx +; SSE2-SSSE3-NEXT: orl %edx, %ecx +; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx +; SSE2-SSSE3-NEXT: shll $15, %edx +; SSE2-SSSE3-NEXT: orl %ecx, %edx +; SSE2-SSSE3-NEXT: orl %eax, %edx +; SSE2-SSSE3-NEXT: movw %dx, (%rdi) +; SSE2-SSSE3-NEXT: retq +; +; AVX1-LABEL: bitcast_16i16_store: +; AVX1: # %bb.0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vpcmpgtw %xmm1, %xmm2, %xmm1 +; AVX1-NEXT: vpcmpgtw %xmm0, %xmm2, %xmm0 +; AVX1-NEXT: vpextrb $2, %xmm0, %eax +; AVX1-NEXT: andl $1, %eax +; AVX1-NEXT: vpextrb $0, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: leal (%rcx,%rax,2), %eax +; AVX1-NEXT: vpextrb $4, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: leal (%rax,%rcx,4), %eax +; AVX1-NEXT: vpextrb $6, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: leal (%rax,%rcx,8), %eax +; AVX1-NEXT: vpextrb $8, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $4, %ecx +; AVX1-NEXT: orl %eax, %ecx +; AVX1-NEXT: vpextrb $10, %xmm0, %eax +; AVX1-NEXT: andl $1, %eax +; AVX1-NEXT: shll $5, %eax +; AVX1-NEXT: orl %ecx, %eax +; AVX1-NEXT: vpextrb $12, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $6, %ecx +; AVX1-NEXT: vpextrb $14, %xmm0, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $7, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $0, %xmm1, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $8, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $2, %xmm1, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $9, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $4, %xmm1, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $10, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $6, %xmm1, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $11, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $8, %xmm1, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $12, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $10, %xmm1, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $13, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $12, %xmm1, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $14, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $14, %xmm1, %edx +; AVX1-NEXT: shll $15, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: orl %eax, %edx +; AVX1-NEXT: movw %dx, (%rdi) +; AVX1-NEXT: vzeroupper +; AVX1-NEXT: retq +; +; AVX2-LABEL: bitcast_16i16_store: +; AVX2: # %bb.0: +; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX2-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm1 +; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm0 +; AVX2-NEXT: vpextrb $2, %xmm1, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: vpextrb $0, %xmm1, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: leal (%rcx,%rax,2), %eax +; AVX2-NEXT: vpextrb $4, %xmm1, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: leal (%rax,%rcx,4), %eax +; AVX2-NEXT: vpextrb $6, %xmm1, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: leal (%rax,%rcx,8), %eax +; AVX2-NEXT: vpextrb $8, %xmm1, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $4, %ecx +; AVX2-NEXT: orl %eax, %ecx +; AVX2-NEXT: vpextrb $10, %xmm1, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: shll $5, %eax +; AVX2-NEXT: orl %ecx, %eax +; AVX2-NEXT: vpextrb $12, %xmm1, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $6, %ecx +; AVX2-NEXT: vpextrb $14, %xmm1, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $7, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $0, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $8, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $2, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $9, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $4, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $10, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $6, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $11, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $8, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $12, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $10, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $13, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $12, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $14, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $14, %xmm0, %edx +; AVX2-NEXT: shll $15, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: orl %eax, %edx +; AVX2-NEXT: movw %dx, (%rdi) +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq +; +; AVX512F-LABEL: bitcast_16i16_store: +; AVX512F: # %bb.0: +; AVX512F-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512F-NEXT: vpcmpgtw %ymm0, %ymm1, %ymm0 +; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0 +; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k0 +; AVX512F-NEXT: kmovw %k0, (%rdi) +; AVX512F-NEXT: vzeroupper +; AVX512F-NEXT: retq +; +; AVX512BW-LABEL: bitcast_16i16_store: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: vpmovw2m %ymm0, %k0 +; AVX512BW-NEXT: kmovw %k0, (%rdi) +; AVX512BW-NEXT: vzeroupper +; AVX512BW-NEXT: retq + %a1 = icmp slt <16 x i16> %a0, zeroinitializer + %a2 = bitcast <16 x i1> %a1 to i16 + store i16 %a2, i16* %p + ret void +} + +define void @bitcast_8i32_store(i8* %p, <8 x i32> %a0) { +; SSE2-SSSE3-LABEL: bitcast_8i32_store: +; SSE2-SSSE3: # %bb.0: +; SSE2-SSSE3-NEXT: pxor %xmm2, %xmm2 +; SSE2-SSSE3-NEXT: pxor %xmm3, %xmm3 +; SSE2-SSSE3-NEXT: pcmpgtd %xmm1, %xmm3 +; SSE2-SSSE3-NEXT: pcmpgtd %xmm0, %xmm2 +; SSE2-SSSE3-NEXT: packssdw %xmm3, %xmm2 +; SSE2-SSSE3-NEXT: packsswb %xmm0, %xmm2 +; SSE2-SSSE3-NEXT: pmovmskb %xmm2, %eax +; SSE2-SSSE3-NEXT: movb %al, (%rdi) +; SSE2-SSSE3-NEXT: retq +; +; AVX12-LABEL: bitcast_8i32_store: +; AVX12: # %bb.0: +; AVX12-NEXT: vmovmskps %ymm0, %eax +; AVX12-NEXT: movb %al, (%rdi) +; AVX12-NEXT: vzeroupper +; AVX12-NEXT: retq +; +; AVX512F-LABEL: bitcast_8i32_store: +; AVX512F: # %bb.0: +; AVX512F-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512F-NEXT: vpcmpgtd %ymm0, %ymm1, %k0 +; AVX512F-NEXT: kmovw %k0, %eax +; AVX512F-NEXT: movb %al, (%rdi) +; AVX512F-NEXT: vzeroupper +; AVX512F-NEXT: retq +; +; AVX512BW-LABEL: bitcast_8i32_store: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512BW-NEXT: vpcmpgtd %ymm0, %ymm1, %k0 +; AVX512BW-NEXT: kmovd %k0, %eax +; AVX512BW-NEXT: movb %al, (%rdi) +; AVX512BW-NEXT: vzeroupper +; AVX512BW-NEXT: retq + %a1 = icmp slt <8 x i32> %a0, zeroinitializer + %a2 = bitcast <8 x i1> %a1 to i8 + store i8 %a2, i8* %p + ret void +} + +define void @bitcast_4i64_store(i4* %p, <4 x i64> %a0) { +; SSE2-SSSE3-LABEL: bitcast_4i64_store: +; SSE2-SSSE3: # %bb.0: +; SSE2-SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648] +; SSE2-SSSE3-NEXT: pxor %xmm2, %xmm1 +; SSE2-SSSE3-NEXT: movdqa %xmm2, %xmm3 +; SSE2-SSSE3-NEXT: pcmpgtd %xmm1, %xmm3 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2] +; SSE2-SSSE3-NEXT: pcmpeqd %xmm2, %xmm1 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] +; SSE2-SSSE3-NEXT: pand %xmm4, %xmm1 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] +; SSE2-SSSE3-NEXT: por %xmm1, %xmm3 +; SSE2-SSSE3-NEXT: pxor %xmm2, %xmm0 +; SSE2-SSSE3-NEXT: movdqa %xmm2, %xmm1 +; SSE2-SSSE3-NEXT: pcmpgtd %xmm0, %xmm1 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm1[0,0,2,2] +; SSE2-SSSE3-NEXT: pcmpeqd %xmm2, %xmm0 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] +; SSE2-SSSE3-NEXT: pand %xmm4, %xmm0 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] +; SSE2-SSSE3-NEXT: por %xmm0, %xmm1 +; SSE2-SSSE3-NEXT: movdqa %xmm1, %xmm0 +; SSE2-SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm3[0,2] +; SSE2-SSSE3-NEXT: movd %xmm1, %eax +; SSE2-SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,2],xmm3[0,2] +; SSE2-SSSE3-NEXT: movd %xmm1, %ecx +; SSE2-SSSE3-NEXT: andb $1, %cl +; SSE2-SSSE3-NEXT: addb %cl, %cl +; SSE2-SSSE3-NEXT: andb $1, %al +; SSE2-SSSE3-NEXT: movd %xmm3, %edx +; SSE2-SSSE3-NEXT: andb $1, %dl +; SSE2-SSSE3-NEXT: shlb $2, %dl +; SSE2-SSSE3-NEXT: orb %cl, %dl +; SSE2-SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3] +; SSE2-SSSE3-NEXT: movd %xmm0, %ecx +; SSE2-SSSE3-NEXT: shlb $3, %cl +; SSE2-SSSE3-NEXT: orb %dl, %cl +; SSE2-SSSE3-NEXT: orb %al, %cl +; SSE2-SSSE3-NEXT: andb $15, %cl +; SSE2-SSSE3-NEXT: movb %cl, (%rdi) +; SSE2-SSSE3-NEXT: retq +; +; AVX1-LABEL: bitcast_4i64_store: +; AVX1: # %bb.0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm1 +; AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm0 +; AVX1-NEXT: vpackssdw %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vmovd %xmm0, %eax +; AVX1-NEXT: andb $1, %al +; AVX1-NEXT: vpextrd $1, %xmm0, %ecx +; AVX1-NEXT: andb $1, %cl +; AVX1-NEXT: addb %cl, %cl +; AVX1-NEXT: vpextrd $2, %xmm0, %edx +; AVX1-NEXT: andb $1, %dl +; AVX1-NEXT: shlb $2, %dl +; AVX1-NEXT: orb %cl, %dl +; AVX1-NEXT: vpextrd $3, %xmm0, %ecx +; AVX1-NEXT: shlb $3, %cl +; AVX1-NEXT: orb %dl, %cl +; AVX1-NEXT: orb %al, %cl +; AVX1-NEXT: andb $15, %cl +; AVX1-NEXT: movb %cl, (%rdi) +; AVX1-NEXT: vzeroupper +; AVX1-NEXT: retq +; +; AVX2-LABEL: bitcast_4i64_store: +; AVX2: # %bb.0: +; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0 +; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 +; AVX2-NEXT: vpackssdw %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vmovd %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: vpextrd $1, %xmm0, %ecx +; AVX2-NEXT: andb $1, %cl +; AVX2-NEXT: addb %cl, %cl +; AVX2-NEXT: vpextrd $2, %xmm0, %edx +; AVX2-NEXT: andb $1, %dl +; AVX2-NEXT: shlb $2, %dl +; AVX2-NEXT: orb %cl, %dl +; AVX2-NEXT: vpextrd $3, %xmm0, %ecx +; AVX2-NEXT: shlb $3, %cl +; AVX2-NEXT: orb %dl, %cl +; AVX2-NEXT: orb %al, %cl +; AVX2-NEXT: andb $15, %cl +; AVX2-NEXT: movb %cl, (%rdi) +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq +; +; AVX512F-LABEL: bitcast_4i64_store: +; AVX512F: # %bb.0: +; AVX512F-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512F-NEXT: vpcmpgtq %ymm0, %ymm1, %k0 +; AVX512F-NEXT: kmovw %k0, %eax +; AVX512F-NEXT: movb %al, (%rdi) +; AVX512F-NEXT: vzeroupper +; AVX512F-NEXT: retq +; +; AVX512BW-LABEL: bitcast_4i64_store: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512BW-NEXT: vpcmpgtq %ymm0, %ymm1, %k0 +; AVX512BW-NEXT: kmovd %k0, %eax +; AVX512BW-NEXT: movb %al, (%rdi) +; AVX512BW-NEXT: vzeroupper +; AVX512BW-NEXT: retq + %a1 = icmp slt <4 x i64> %a0, zeroinitializer + %a2 = bitcast <4 x i1> %a1 to i4 + store i4 %a2, i4* %p + ret void +} diff --git a/llvm/test/CodeGen/X86/bitcast-setcc-512.ll b/llvm/test/CodeGen/X86/bitcast-setcc-512.ll index 743172a6f47f..ebbc37158661 100644 --- a/llvm/test/CodeGen/X86/bitcast-setcc-512.ll +++ b/llvm/test/CodeGen/X86/bitcast-setcc-512.ll @@ -415,3 +415,1521 @@ define i8 @v8f64(<8 x double> %a, <8 x double> %b) { %res = bitcast <8 x i1> %x to i8 ret i8 %res } + +define void @bitcast_64i8_store(i64* %p, <64 x i8> %a0) { +; SSE-LABEL: bitcast_64i8_store: +; SSE: # %bb.0: +; SSE-NEXT: pxor %xmm5, %xmm5 +; SSE-NEXT: pxor %xmm4, %xmm4 +; SSE-NEXT: pcmpgtb %xmm0, %xmm4 +; SSE-NEXT: pxor %xmm0, %xmm0 +; SSE-NEXT: pcmpgtb %xmm1, %xmm0 +; SSE-NEXT: pxor %xmm1, %xmm1 +; SSE-NEXT: pcmpgtb %xmm2, %xmm1 +; SSE-NEXT: pcmpgtb %xmm3, %xmm5 +; SSE-NEXT: pextrb $1, %xmm5, %eax +; SSE-NEXT: andl $1, %eax +; SSE-NEXT: pextrb $0, %xmm5, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: leal (%rcx,%rax,2), %eax +; SSE-NEXT: pextrb $2, %xmm5, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: leal (%rax,%rcx,4), %eax +; SSE-NEXT: pextrb $3, %xmm5, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: leal (%rax,%rcx,8), %eax +; SSE-NEXT: pextrb $4, %xmm5, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $4, %ecx +; SSE-NEXT: orl %eax, %ecx +; SSE-NEXT: pextrb $5, %xmm5, %eax +; SSE-NEXT: andl $1, %eax +; SSE-NEXT: shll $5, %eax +; SSE-NEXT: orl %ecx, %eax +; SSE-NEXT: pextrb $6, %xmm5, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $6, %ecx +; SSE-NEXT: pextrb $7, %xmm5, %edx +; SSE-NEXT: andl $1, %edx +; SSE-NEXT: shll $7, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: pextrb $8, %xmm5, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $8, %ecx +; SSE-NEXT: orl %edx, %ecx +; SSE-NEXT: pextrb $9, %xmm5, %edx +; SSE-NEXT: andl $1, %edx +; SSE-NEXT: shll $9, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: pextrb $10, %xmm5, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $10, %ecx +; SSE-NEXT: orl %edx, %ecx +; SSE-NEXT: pextrb $11, %xmm5, %edx +; SSE-NEXT: andl $1, %edx +; SSE-NEXT: shll $11, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: pextrb $12, %xmm5, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $12, %ecx +; SSE-NEXT: orl %edx, %ecx +; SSE-NEXT: pextrb $13, %xmm5, %edx +; SSE-NEXT: andl $1, %edx +; SSE-NEXT: shll $13, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: pextrb $14, %xmm5, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $14, %ecx +; SSE-NEXT: orl %edx, %ecx +; SSE-NEXT: pextrb $15, %xmm5, %edx +; SSE-NEXT: shll $15, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: orl %eax, %edx +; SSE-NEXT: movw %dx, 6(%rdi) +; SSE-NEXT: pextrb $1, %xmm1, %eax +; SSE-NEXT: andl $1, %eax +; SSE-NEXT: pextrb $0, %xmm1, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: leal (%rcx,%rax,2), %eax +; SSE-NEXT: pextrb $2, %xmm1, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: leal (%rax,%rcx,4), %eax +; SSE-NEXT: pextrb $3, %xmm1, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: leal (%rax,%rcx,8), %eax +; SSE-NEXT: pextrb $4, %xmm1, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $4, %ecx +; SSE-NEXT: orl %eax, %ecx +; SSE-NEXT: pextrb $5, %xmm1, %eax +; SSE-NEXT: andl $1, %eax +; SSE-NEXT: shll $5, %eax +; SSE-NEXT: orl %ecx, %eax +; SSE-NEXT: pextrb $6, %xmm1, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $6, %ecx +; SSE-NEXT: pextrb $7, %xmm1, %edx +; SSE-NEXT: andl $1, %edx +; SSE-NEXT: shll $7, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: pextrb $8, %xmm1, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $8, %ecx +; SSE-NEXT: orl %edx, %ecx +; SSE-NEXT: pextrb $9, %xmm1, %edx +; SSE-NEXT: andl $1, %edx +; SSE-NEXT: shll $9, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: pextrb $10, %xmm1, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $10, %ecx +; SSE-NEXT: orl %edx, %ecx +; SSE-NEXT: pextrb $11, %xmm1, %edx +; SSE-NEXT: andl $1, %edx +; SSE-NEXT: shll $11, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: pextrb $12, %xmm1, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $12, %ecx +; SSE-NEXT: orl %edx, %ecx +; SSE-NEXT: pextrb $13, %xmm1, %edx +; SSE-NEXT: andl $1, %edx +; SSE-NEXT: shll $13, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: pextrb $14, %xmm1, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $14, %ecx +; SSE-NEXT: orl %edx, %ecx +; SSE-NEXT: pextrb $15, %xmm1, %edx +; SSE-NEXT: shll $15, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: orl %eax, %edx +; SSE-NEXT: movw %dx, 4(%rdi) +; SSE-NEXT: pextrb $1, %xmm0, %eax +; SSE-NEXT: andl $1, %eax +; SSE-NEXT: pextrb $0, %xmm0, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: leal (%rcx,%rax,2), %eax +; SSE-NEXT: pextrb $2, %xmm0, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: leal (%rax,%rcx,4), %eax +; SSE-NEXT: pextrb $3, %xmm0, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: leal (%rax,%rcx,8), %eax +; SSE-NEXT: pextrb $4, %xmm0, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $4, %ecx +; SSE-NEXT: orl %eax, %ecx +; SSE-NEXT: pextrb $5, %xmm0, %eax +; SSE-NEXT: andl $1, %eax +; SSE-NEXT: shll $5, %eax +; SSE-NEXT: orl %ecx, %eax +; SSE-NEXT: pextrb $6, %xmm0, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $6, %ecx +; SSE-NEXT: pextrb $7, %xmm0, %edx +; SSE-NEXT: andl $1, %edx +; SSE-NEXT: shll $7, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: pextrb $8, %xmm0, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $8, %ecx +; SSE-NEXT: orl %edx, %ecx +; SSE-NEXT: pextrb $9, %xmm0, %edx +; SSE-NEXT: andl $1, %edx +; SSE-NEXT: shll $9, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: pextrb $10, %xmm0, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $10, %ecx +; SSE-NEXT: orl %edx, %ecx +; SSE-NEXT: pextrb $11, %xmm0, %edx +; SSE-NEXT: andl $1, %edx +; SSE-NEXT: shll $11, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: pextrb $12, %xmm0, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $12, %ecx +; SSE-NEXT: orl %edx, %ecx +; SSE-NEXT: pextrb $13, %xmm0, %edx +; SSE-NEXT: andl $1, %edx +; SSE-NEXT: shll $13, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: pextrb $14, %xmm0, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $14, %ecx +; SSE-NEXT: orl %edx, %ecx +; SSE-NEXT: pextrb $15, %xmm0, %edx +; SSE-NEXT: shll $15, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: orl %eax, %edx +; SSE-NEXT: movw %dx, 2(%rdi) +; SSE-NEXT: pextrb $1, %xmm4, %eax +; SSE-NEXT: andl $1, %eax +; SSE-NEXT: pextrb $0, %xmm4, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: leal (%rcx,%rax,2), %eax +; SSE-NEXT: pextrb $2, %xmm4, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: leal (%rax,%rcx,4), %eax +; SSE-NEXT: pextrb $3, %xmm4, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: leal (%rax,%rcx,8), %eax +; SSE-NEXT: pextrb $4, %xmm4, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $4, %ecx +; SSE-NEXT: orl %eax, %ecx +; SSE-NEXT: pextrb $5, %xmm4, %eax +; SSE-NEXT: andl $1, %eax +; SSE-NEXT: shll $5, %eax +; SSE-NEXT: orl %ecx, %eax +; SSE-NEXT: pextrb $6, %xmm4, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $6, %ecx +; SSE-NEXT: pextrb $7, %xmm4, %edx +; SSE-NEXT: andl $1, %edx +; SSE-NEXT: shll $7, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: pextrb $8, %xmm4, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $8, %ecx +; SSE-NEXT: orl %edx, %ecx +; SSE-NEXT: pextrb $9, %xmm4, %edx +; SSE-NEXT: andl $1, %edx +; SSE-NEXT: shll $9, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: pextrb $10, %xmm4, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $10, %ecx +; SSE-NEXT: orl %edx, %ecx +; SSE-NEXT: pextrb $11, %xmm4, %edx +; SSE-NEXT: andl $1, %edx +; SSE-NEXT: shll $11, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: pextrb $12, %xmm4, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $12, %ecx +; SSE-NEXT: orl %edx, %ecx +; SSE-NEXT: pextrb $13, %xmm4, %edx +; SSE-NEXT: andl $1, %edx +; SSE-NEXT: shll $13, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: pextrb $14, %xmm4, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $14, %ecx +; SSE-NEXT: orl %edx, %ecx +; SSE-NEXT: pextrb $15, %xmm4, %edx +; SSE-NEXT: shll $15, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: orl %eax, %edx +; SSE-NEXT: movw %dx, (%rdi) +; SSE-NEXT: retq +; +; AVX1-LABEL: bitcast_64i8_store: +; AVX1: # %bb.0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4 +; AVX1-NEXT: vpcmpgtb %xmm2, %xmm4, %xmm2 +; AVX1-NEXT: vpcmpgtb %xmm0, %xmm4, %xmm0 +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3 +; AVX1-NEXT: vpcmpgtb %xmm3, %xmm4, %xmm3 +; AVX1-NEXT: vpcmpgtb %xmm1, %xmm4, %xmm1 +; AVX1-NEXT: vpextrb $1, %xmm1, %eax +; AVX1-NEXT: andl $1, %eax +; AVX1-NEXT: vpextrb $0, %xmm1, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: leal (%rcx,%rax,2), %eax +; AVX1-NEXT: vpextrb $2, %xmm1, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: leal (%rax,%rcx,4), %eax +; AVX1-NEXT: vpextrb $3, %xmm1, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: leal (%rax,%rcx,8), %eax +; AVX1-NEXT: vpextrb $4, %xmm1, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $4, %ecx +; AVX1-NEXT: orl %eax, %ecx +; AVX1-NEXT: vpextrb $5, %xmm1, %eax +; AVX1-NEXT: andl $1, %eax +; AVX1-NEXT: shll $5, %eax +; AVX1-NEXT: orl %ecx, %eax +; AVX1-NEXT: vpextrb $6, %xmm1, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $6, %ecx +; AVX1-NEXT: vpextrb $7, %xmm1, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $7, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $8, %xmm1, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $8, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $9, %xmm1, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $9, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $10, %xmm1, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $10, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $11, %xmm1, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $11, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $12, %xmm1, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $12, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $13, %xmm1, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $13, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $14, %xmm1, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $14, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $15, %xmm1, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $15, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $0, %xmm3, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $16, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $1, %xmm3, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $17, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $2, %xmm3, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $18, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $3, %xmm3, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $19, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $4, %xmm3, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $20, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $5, %xmm3, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $21, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $6, %xmm3, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $22, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $7, %xmm3, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $23, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $8, %xmm3, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $24, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $9, %xmm3, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $25, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $10, %xmm3, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $26, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $11, %xmm3, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $27, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $12, %xmm3, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $28, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $13, %xmm3, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $29, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $14, %xmm3, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $30, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $15, %xmm3, %edx +; AVX1-NEXT: shll $31, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: orl %eax, %edx +; AVX1-NEXT: movl %edx, 4(%rdi) +; AVX1-NEXT: vpextrb $1, %xmm0, %eax +; AVX1-NEXT: andl $1, %eax +; AVX1-NEXT: vpextrb $0, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: leal (%rcx,%rax,2), %eax +; AVX1-NEXT: vpextrb $2, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: leal (%rax,%rcx,4), %eax +; AVX1-NEXT: vpextrb $3, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: leal (%rax,%rcx,8), %eax +; AVX1-NEXT: vpextrb $4, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $4, %ecx +; AVX1-NEXT: orl %eax, %ecx +; AVX1-NEXT: vpextrb $5, %xmm0, %eax +; AVX1-NEXT: andl $1, %eax +; AVX1-NEXT: shll $5, %eax +; AVX1-NEXT: orl %ecx, %eax +; AVX1-NEXT: vpextrb $6, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $6, %ecx +; AVX1-NEXT: vpextrb $7, %xmm0, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $7, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $8, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $8, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $9, %xmm0, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $9, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $10, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $10, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $11, %xmm0, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $11, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $12, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $12, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $13, %xmm0, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $13, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $14, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $14, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $15, %xmm0, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $15, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $0, %xmm2, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $16, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $1, %xmm2, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $17, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $2, %xmm2, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $18, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $3, %xmm2, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $19, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $4, %xmm2, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $20, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $5, %xmm2, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $21, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $6, %xmm2, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $22, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $7, %xmm2, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $23, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $8, %xmm2, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $24, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $9, %xmm2, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $25, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $10, %xmm2, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $26, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $11, %xmm2, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $27, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $12, %xmm2, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $28, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $13, %xmm2, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $29, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $14, %xmm2, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $30, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $15, %xmm2, %edx +; AVX1-NEXT: shll $31, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: orl %eax, %edx +; AVX1-NEXT: movl %edx, (%rdi) +; AVX1-NEXT: vzeroupper +; AVX1-NEXT: retq +; +; AVX2-LABEL: bitcast_64i8_store: +; AVX2: # %bb.0: +; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX2-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm0 +; AVX2-NEXT: vpcmpgtb %ymm1, %ymm2, %ymm1 +; AVX2-NEXT: vpextrb $1, %xmm1, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: vpextrb $0, %xmm1, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: leal (%rcx,%rax,2), %eax +; AVX2-NEXT: vpextrb $2, %xmm1, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: leal (%rax,%rcx,4), %eax +; AVX2-NEXT: vpextrb $3, %xmm1, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: leal (%rax,%rcx,8), %eax +; AVX2-NEXT: vpextrb $4, %xmm1, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $4, %ecx +; AVX2-NEXT: orl %eax, %ecx +; AVX2-NEXT: vpextrb $5, %xmm1, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: shll $5, %eax +; AVX2-NEXT: orl %ecx, %eax +; AVX2-NEXT: vpextrb $6, %xmm1, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $6, %ecx +; AVX2-NEXT: vpextrb $7, %xmm1, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $7, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $8, %xmm1, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $8, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $9, %xmm1, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $9, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $10, %xmm1, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $10, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $11, %xmm1, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $11, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $12, %xmm1, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $12, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $13, %xmm1, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $13, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $14, %xmm1, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $14, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $15, %xmm1, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $15, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm1 +; AVX2-NEXT: vpextrb $0, %xmm1, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $16, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $1, %xmm1, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $17, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $2, %xmm1, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $18, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $3, %xmm1, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $19, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $4, %xmm1, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $20, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $5, %xmm1, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $21, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $6, %xmm1, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $22, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $7, %xmm1, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $23, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $8, %xmm1, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $24, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $9, %xmm1, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $25, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $10, %xmm1, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $26, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $11, %xmm1, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $27, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $12, %xmm1, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $28, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $13, %xmm1, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $29, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $14, %xmm1, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $30, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $15, %xmm1, %edx +; AVX2-NEXT: shll $31, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: orl %eax, %edx +; AVX2-NEXT: movl %edx, 4(%rdi) +; AVX2-NEXT: vpextrb $1, %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: vpextrb $0, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: leal (%rcx,%rax,2), %eax +; AVX2-NEXT: vpextrb $2, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: leal (%rax,%rcx,4), %eax +; AVX2-NEXT: vpextrb $3, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: leal (%rax,%rcx,8), %eax +; AVX2-NEXT: vpextrb $4, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $4, %ecx +; AVX2-NEXT: orl %eax, %ecx +; AVX2-NEXT: vpextrb $5, %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: shll $5, %eax +; AVX2-NEXT: orl %ecx, %eax +; AVX2-NEXT: vpextrb $6, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $6, %ecx +; AVX2-NEXT: vpextrb $7, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $7, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $8, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $8, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $9, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $9, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $10, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $10, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $11, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $11, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $12, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $12, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $13, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $13, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $14, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $14, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $15, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $15, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 +; AVX2-NEXT: vpextrb $0, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $16, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $1, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $17, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $2, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $18, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $3, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $19, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $4, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $20, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $5, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $21, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $6, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $22, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $7, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $23, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $8, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $24, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $9, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $25, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $10, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $26, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $11, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $27, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $12, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $28, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $13, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $29, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $14, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $30, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $15, %xmm0, %edx +; AVX2-NEXT: shll $31, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: orl %eax, %edx +; AVX2-NEXT: movl %edx, (%rdi) +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq +; +; AVX512F-LABEL: bitcast_64i8_store: +; AVX512F: # %bb.0: +; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX512F-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm0 +; AVX512F-NEXT: vpmovsxbd %xmm0, %zmm3 +; AVX512F-NEXT: vptestmd %zmm3, %zmm3, %k0 +; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0 +; AVX512F-NEXT: vpmovsxbd %xmm0, %zmm0 +; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k1 +; AVX512F-NEXT: vpcmpgtb %ymm1, %ymm2, %ymm0 +; AVX512F-NEXT: vpmovsxbd %xmm0, %zmm1 +; AVX512F-NEXT: vptestmd %zmm1, %zmm1, %k2 +; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0 +; AVX512F-NEXT: vpmovsxbd %xmm0, %zmm0 +; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k3 +; AVX512F-NEXT: kmovw %k3, 6(%rdi) +; AVX512F-NEXT: kmovw %k2, 4(%rdi) +; AVX512F-NEXT: kmovw %k1, 2(%rdi) +; AVX512F-NEXT: kmovw %k0, (%rdi) +; AVX512F-NEXT: vzeroupper +; AVX512F-NEXT: retq +; +; AVX512BW-LABEL: bitcast_64i8_store: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: vpmovb2m %zmm0, %k0 +; AVX512BW-NEXT: kmovq %k0, (%rdi) +; AVX512BW-NEXT: vzeroupper +; AVX512BW-NEXT: retq + %a1 = icmp slt <64 x i8> %a0, zeroinitializer + %a2 = bitcast <64 x i1> %a1 to i64 + store i64 %a2, i64* %p + ret void +} + +define void @bitcast_32i16_store(i32* %p, <32 x i16> %a0) { +; SSE-LABEL: bitcast_32i16_store: +; SSE: # %bb.0: +; SSE-NEXT: pxor %xmm5, %xmm5 +; SSE-NEXT: pxor %xmm4, %xmm4 +; SSE-NEXT: pcmpgtw %xmm1, %xmm4 +; SSE-NEXT: pxor %xmm1, %xmm1 +; SSE-NEXT: pcmpgtw %xmm0, %xmm1 +; SSE-NEXT: pxor %xmm0, %xmm0 +; SSE-NEXT: pcmpgtw %xmm3, %xmm0 +; SSE-NEXT: pcmpgtw %xmm2, %xmm5 +; SSE-NEXT: pextrb $2, %xmm5, %eax +; SSE-NEXT: andl $1, %eax +; SSE-NEXT: pextrb $0, %xmm5, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: leal (%rcx,%rax,2), %eax +; SSE-NEXT: pextrb $4, %xmm5, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: leal (%rax,%rcx,4), %eax +; SSE-NEXT: pextrb $6, %xmm5, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: leal (%rax,%rcx,8), %eax +; SSE-NEXT: pextrb $8, %xmm5, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $4, %ecx +; SSE-NEXT: orl %eax, %ecx +; SSE-NEXT: pextrb $10, %xmm5, %eax +; SSE-NEXT: andl $1, %eax +; SSE-NEXT: shll $5, %eax +; SSE-NEXT: orl %ecx, %eax +; SSE-NEXT: pextrb $12, %xmm5, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $6, %ecx +; SSE-NEXT: pextrb $14, %xmm5, %edx +; SSE-NEXT: andl $1, %edx +; SSE-NEXT: shll $7, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: pextrb $0, %xmm0, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $8, %ecx +; SSE-NEXT: orl %edx, %ecx +; SSE-NEXT: pextrb $2, %xmm0, %edx +; SSE-NEXT: andl $1, %edx +; SSE-NEXT: shll $9, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: pextrb $4, %xmm0, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $10, %ecx +; SSE-NEXT: orl %edx, %ecx +; SSE-NEXT: pextrb $6, %xmm0, %edx +; SSE-NEXT: andl $1, %edx +; SSE-NEXT: shll $11, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: pextrb $8, %xmm0, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $12, %ecx +; SSE-NEXT: orl %edx, %ecx +; SSE-NEXT: pextrb $10, %xmm0, %edx +; SSE-NEXT: andl $1, %edx +; SSE-NEXT: shll $13, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: pextrb $12, %xmm0, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $14, %ecx +; SSE-NEXT: orl %edx, %ecx +; SSE-NEXT: pextrb $14, %xmm0, %edx +; SSE-NEXT: shll $15, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: orl %eax, %edx +; SSE-NEXT: movw %dx, 2(%rdi) +; SSE-NEXT: pextrb $2, %xmm1, %eax +; SSE-NEXT: andl $1, %eax +; SSE-NEXT: pextrb $0, %xmm1, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: leal (%rcx,%rax,2), %eax +; SSE-NEXT: pextrb $4, %xmm1, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: leal (%rax,%rcx,4), %eax +; SSE-NEXT: pextrb $6, %xmm1, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: leal (%rax,%rcx,8), %eax +; SSE-NEXT: pextrb $8, %xmm1, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $4, %ecx +; SSE-NEXT: orl %eax, %ecx +; SSE-NEXT: pextrb $10, %xmm1, %eax +; SSE-NEXT: andl $1, %eax +; SSE-NEXT: shll $5, %eax +; SSE-NEXT: orl %ecx, %eax +; SSE-NEXT: pextrb $12, %xmm1, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $6, %ecx +; SSE-NEXT: pextrb $14, %xmm1, %edx +; SSE-NEXT: andl $1, %edx +; SSE-NEXT: shll $7, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: pextrb $0, %xmm4, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $8, %ecx +; SSE-NEXT: orl %edx, %ecx +; SSE-NEXT: pextrb $2, %xmm4, %edx +; SSE-NEXT: andl $1, %edx +; SSE-NEXT: shll $9, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: pextrb $4, %xmm4, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $10, %ecx +; SSE-NEXT: orl %edx, %ecx +; SSE-NEXT: pextrb $6, %xmm4, %edx +; SSE-NEXT: andl $1, %edx +; SSE-NEXT: shll $11, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: pextrb $8, %xmm4, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $12, %ecx +; SSE-NEXT: orl %edx, %ecx +; SSE-NEXT: pextrb $10, %xmm4, %edx +; SSE-NEXT: andl $1, %edx +; SSE-NEXT: shll $13, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: pextrb $12, %xmm4, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $14, %ecx +; SSE-NEXT: orl %edx, %ecx +; SSE-NEXT: pextrb $14, %xmm4, %edx +; SSE-NEXT: shll $15, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: orl %eax, %edx +; SSE-NEXT: movw %dx, (%rdi) +; SSE-NEXT: retq +; +; AVX1-LABEL: bitcast_32i16_store: +; AVX1: # %bb.0: +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 +; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4 +; AVX1-NEXT: vpcmpgtw %xmm2, %xmm4, %xmm2 +; AVX1-NEXT: vpcmpgtw %xmm1, %xmm4, %xmm1 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 +; AVX1-NEXT: vpcmpgtw %xmm3, %xmm4, %xmm3 +; AVX1-NEXT: vpcmpgtw %xmm0, %xmm4, %xmm0 +; AVX1-NEXT: vpextrb $2, %xmm0, %eax +; AVX1-NEXT: andl $1, %eax +; AVX1-NEXT: vpextrb $0, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: leal (%rcx,%rax,2), %eax +; AVX1-NEXT: vpextrb $4, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: leal (%rax,%rcx,4), %eax +; AVX1-NEXT: vpextrb $6, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: leal (%rax,%rcx,8), %eax +; AVX1-NEXT: vpextrb $8, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $4, %ecx +; AVX1-NEXT: orl %eax, %ecx +; AVX1-NEXT: vpextrb $10, %xmm0, %eax +; AVX1-NEXT: andl $1, %eax +; AVX1-NEXT: shll $5, %eax +; AVX1-NEXT: orl %ecx, %eax +; AVX1-NEXT: vpextrb $12, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $6, %ecx +; AVX1-NEXT: vpextrb $14, %xmm0, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $7, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $0, %xmm3, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $8, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $2, %xmm3, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $9, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $4, %xmm3, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $10, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $6, %xmm3, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $11, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $8, %xmm3, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $12, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $10, %xmm3, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $13, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $12, %xmm3, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $14, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $14, %xmm3, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $15, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $0, %xmm1, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $16, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $2, %xmm1, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $17, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $4, %xmm1, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $18, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $6, %xmm1, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $19, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $8, %xmm1, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $20, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $10, %xmm1, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $21, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $12, %xmm1, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $22, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $14, %xmm1, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $23, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $0, %xmm2, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $24, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $2, %xmm2, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $25, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $4, %xmm2, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $26, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $6, %xmm2, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $27, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $8, %xmm2, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $28, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $10, %xmm2, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $29, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $12, %xmm2, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $30, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $14, %xmm2, %edx +; AVX1-NEXT: shll $31, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: orl %eax, %edx +; AVX1-NEXT: movl %edx, (%rdi) +; AVX1-NEXT: vzeroupper +; AVX1-NEXT: retq +; +; AVX2-LABEL: bitcast_32i16_store: +; AVX2: # %bb.0: +; AVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3 +; AVX2-NEXT: vpcmpgtw %ymm1, %ymm3, %ymm2 +; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm1 +; AVX2-NEXT: vpcmpgtw %ymm0, %ymm3, %ymm3 +; AVX2-NEXT: vextracti128 $1, %ymm3, %xmm0 +; AVX2-NEXT: vpextrb $2, %xmm3, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: vpextrb $0, %xmm3, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: leal (%rcx,%rax,2), %eax +; AVX2-NEXT: vpextrb $4, %xmm3, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: leal (%rax,%rcx,4), %eax +; AVX2-NEXT: vpextrb $6, %xmm3, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: leal (%rax,%rcx,8), %eax +; AVX2-NEXT: vpextrb $8, %xmm3, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $4, %ecx +; AVX2-NEXT: orl %eax, %ecx +; AVX2-NEXT: vpextrb $10, %xmm3, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: shll $5, %eax +; AVX2-NEXT: orl %ecx, %eax +; AVX2-NEXT: vpextrb $12, %xmm3, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $6, %ecx +; AVX2-NEXT: vpextrb $14, %xmm3, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $7, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $0, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $8, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $2, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $9, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $4, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $10, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $6, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $11, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $8, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $12, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $10, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $13, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $12, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $14, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $14, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $15, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $0, %xmm2, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $16, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $2, %xmm2, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $17, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $4, %xmm2, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $18, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $6, %xmm2, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $19, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $8, %xmm2, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $20, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $10, %xmm2, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $21, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $12, %xmm2, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $22, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $14, %xmm2, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $23, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $0, %xmm1, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $24, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $2, %xmm1, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $25, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $4, %xmm1, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $26, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $6, %xmm1, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $27, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $8, %xmm1, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $28, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $10, %xmm1, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $29, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $12, %xmm1, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $30, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $14, %xmm1, %edx +; AVX2-NEXT: shll $31, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: orl %eax, %edx +; AVX2-NEXT: movl %edx, (%rdi) +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq +; +; AVX512F-LABEL: bitcast_32i16_store: +; AVX512F: # %bb.0: +; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX512F-NEXT: vpcmpgtw %ymm0, %ymm2, %ymm0 +; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0 +; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k0 +; AVX512F-NEXT: vpcmpgtw %ymm1, %ymm2, %ymm0 +; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0 +; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k1 +; AVX512F-NEXT: kmovw %k1, 2(%rdi) +; AVX512F-NEXT: kmovw %k0, (%rdi) +; AVX512F-NEXT: vzeroupper +; AVX512F-NEXT: retq +; +; AVX512BW-LABEL: bitcast_32i16_store: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: vpmovw2m %zmm0, %k0 +; AVX512BW-NEXT: kmovd %k0, (%rdi) +; AVX512BW-NEXT: vzeroupper +; AVX512BW-NEXT: retq + %a1 = icmp slt <32 x i16> %a0, zeroinitializer + %a2 = bitcast <32 x i1> %a1 to i32 + store i32 %a2, i32* %p + ret void +} + +define void @bitcast_16i32_store(i16* %p, <16 x i32> %a0) { +; SSE-LABEL: bitcast_16i32_store: +; SSE: # %bb.0: +; SSE-NEXT: pxor %xmm5, %xmm5 +; SSE-NEXT: pxor %xmm4, %xmm4 +; SSE-NEXT: pcmpgtd %xmm3, %xmm4 +; SSE-NEXT: pxor %xmm3, %xmm3 +; SSE-NEXT: pcmpgtd %xmm2, %xmm3 +; SSE-NEXT: pxor %xmm2, %xmm2 +; SSE-NEXT: pcmpgtd %xmm1, %xmm2 +; SSE-NEXT: pcmpgtd %xmm0, %xmm5 +; SSE-NEXT: pextrb $4, %xmm5, %eax +; SSE-NEXT: andl $1, %eax +; SSE-NEXT: pextrb $0, %xmm5, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: leal (%rcx,%rax,2), %eax +; SSE-NEXT: pextrb $8, %xmm5, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: leal (%rax,%rcx,4), %eax +; SSE-NEXT: pextrb $12, %xmm5, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: leal (%rax,%rcx,8), %eax +; SSE-NEXT: pextrb $0, %xmm2, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $4, %ecx +; SSE-NEXT: orl %eax, %ecx +; SSE-NEXT: pextrb $4, %xmm2, %eax +; SSE-NEXT: andl $1, %eax +; SSE-NEXT: shll $5, %eax +; SSE-NEXT: orl %ecx, %eax +; SSE-NEXT: pextrb $8, %xmm2, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $6, %ecx +; SSE-NEXT: pextrb $12, %xmm2, %edx +; SSE-NEXT: andl $1, %edx +; SSE-NEXT: shll $7, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: pextrb $0, %xmm3, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $8, %ecx +; SSE-NEXT: orl %edx, %ecx +; SSE-NEXT: pextrb $4, %xmm3, %edx +; SSE-NEXT: andl $1, %edx +; SSE-NEXT: shll $9, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: pextrb $8, %xmm3, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $10, %ecx +; SSE-NEXT: orl %edx, %ecx +; SSE-NEXT: pextrb $12, %xmm3, %edx +; SSE-NEXT: andl $1, %edx +; SSE-NEXT: shll $11, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: pextrb $0, %xmm4, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $12, %ecx +; SSE-NEXT: orl %edx, %ecx +; SSE-NEXT: pextrb $4, %xmm4, %edx +; SSE-NEXT: andl $1, %edx +; SSE-NEXT: shll $13, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: pextrb $8, %xmm4, %ecx +; SSE-NEXT: andl $1, %ecx +; SSE-NEXT: shll $14, %ecx +; SSE-NEXT: orl %edx, %ecx +; SSE-NEXT: pextrb $12, %xmm4, %edx +; SSE-NEXT: shll $15, %edx +; SSE-NEXT: orl %ecx, %edx +; SSE-NEXT: orl %eax, %edx +; SSE-NEXT: movw %dx, (%rdi) +; SSE-NEXT: retq +; +; AVX1-LABEL: bitcast_16i32_store: +; AVX1: # %bb.0: +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 +; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4 +; AVX1-NEXT: vpcmpgtd %xmm2, %xmm4, %xmm2 +; AVX1-NEXT: vpcmpgtd %xmm1, %xmm4, %xmm1 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 +; AVX1-NEXT: vpcmpgtd %xmm3, %xmm4, %xmm3 +; AVX1-NEXT: vpcmpgtd %xmm0, %xmm4, %xmm0 +; AVX1-NEXT: vpextrb $4, %xmm0, %eax +; AVX1-NEXT: andl $1, %eax +; AVX1-NEXT: vpextrb $0, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: leal (%rcx,%rax,2), %eax +; AVX1-NEXT: vpextrb $8, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: leal (%rax,%rcx,4), %eax +; AVX1-NEXT: vpextrb $12, %xmm0, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: leal (%rax,%rcx,8), %eax +; AVX1-NEXT: vpextrb $0, %xmm3, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $4, %ecx +; AVX1-NEXT: orl %eax, %ecx +; AVX1-NEXT: vpextrb $4, %xmm3, %eax +; AVX1-NEXT: andl $1, %eax +; AVX1-NEXT: shll $5, %eax +; AVX1-NEXT: orl %ecx, %eax +; AVX1-NEXT: vpextrb $8, %xmm3, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $6, %ecx +; AVX1-NEXT: vpextrb $12, %xmm3, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $7, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $0, %xmm1, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $8, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $4, %xmm1, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $9, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $8, %xmm1, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $10, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $12, %xmm1, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $11, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $0, %xmm2, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $12, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $4, %xmm2, %edx +; AVX1-NEXT: andl $1, %edx +; AVX1-NEXT: shll $13, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: vpextrb $8, %xmm2, %ecx +; AVX1-NEXT: andl $1, %ecx +; AVX1-NEXT: shll $14, %ecx +; AVX1-NEXT: orl %edx, %ecx +; AVX1-NEXT: vpextrb $12, %xmm2, %edx +; AVX1-NEXT: shll $15, %edx +; AVX1-NEXT: orl %ecx, %edx +; AVX1-NEXT: orl %eax, %edx +; AVX1-NEXT: movw %dx, (%rdi) +; AVX1-NEXT: vzeroupper +; AVX1-NEXT: retq +; +; AVX2-LABEL: bitcast_16i32_store: +; AVX2: # %bb.0: +; AVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3 +; AVX2-NEXT: vpcmpgtd %ymm1, %ymm3, %ymm2 +; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm1 +; AVX2-NEXT: vpcmpgtd %ymm0, %ymm3, %ymm3 +; AVX2-NEXT: vextracti128 $1, %ymm3, %xmm0 +; AVX2-NEXT: vpextrb $4, %xmm3, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: vpextrb $0, %xmm3, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: leal (%rcx,%rax,2), %eax +; AVX2-NEXT: vpextrb $8, %xmm3, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: leal (%rax,%rcx,4), %eax +; AVX2-NEXT: vpextrb $12, %xmm3, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: leal (%rax,%rcx,8), %eax +; AVX2-NEXT: vpextrb $0, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $4, %ecx +; AVX2-NEXT: orl %eax, %ecx +; AVX2-NEXT: vpextrb $4, %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: shll $5, %eax +; AVX2-NEXT: orl %ecx, %eax +; AVX2-NEXT: vpextrb $8, %xmm0, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $6, %ecx +; AVX2-NEXT: vpextrb $12, %xmm0, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $7, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $0, %xmm2, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $8, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $4, %xmm2, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $9, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $8, %xmm2, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $10, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $12, %xmm2, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $11, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $0, %xmm1, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $12, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $4, %xmm1, %edx +; AVX2-NEXT: andl $1, %edx +; AVX2-NEXT: shll $13, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: vpextrb $8, %xmm1, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: shll $14, %ecx +; AVX2-NEXT: orl %edx, %ecx +; AVX2-NEXT: vpextrb $12, %xmm1, %edx +; AVX2-NEXT: shll $15, %edx +; AVX2-NEXT: orl %ecx, %edx +; AVX2-NEXT: orl %eax, %edx +; AVX2-NEXT: movw %dx, (%rdi) +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq +; +; AVX512-LABEL: bitcast_16i32_store: +; AVX512: # %bb.0: +; AVX512-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512-NEXT: vpcmpgtd %zmm0, %zmm1, %k0 +; AVX512-NEXT: kmovw %k0, (%rdi) +; AVX512-NEXT: vzeroupper +; AVX512-NEXT: retq + %a1 = icmp slt <16 x i32> %a0, zeroinitializer + %a2 = bitcast <16 x i1> %a1 to i16 + store i16 %a2, i16* %p + ret void +} + +define void @bitcast_8i64_store(i8* %p, <8 x i64> %a0) { +; SSE-LABEL: bitcast_8i64_store: +; SSE: # %bb.0: +; SSE-NEXT: pxor %xmm4, %xmm4 +; SSE-NEXT: pxor %xmm5, %xmm5 +; SSE-NEXT: pcmpgtq %xmm3, %xmm5 +; SSE-NEXT: pxor %xmm3, %xmm3 +; SSE-NEXT: pcmpgtq %xmm2, %xmm3 +; SSE-NEXT: packssdw %xmm5, %xmm3 +; SSE-NEXT: pxor %xmm2, %xmm2 +; SSE-NEXT: pcmpgtq %xmm1, %xmm2 +; SSE-NEXT: pcmpgtq %xmm0, %xmm4 +; SSE-NEXT: packssdw %xmm2, %xmm4 +; SSE-NEXT: packssdw %xmm3, %xmm4 +; SSE-NEXT: packsswb %xmm0, %xmm4 +; SSE-NEXT: pmovmskb %xmm4, %eax +; SSE-NEXT: movb %al, (%rdi) +; SSE-NEXT: retq +; +; AVX1-LABEL: bitcast_8i64_store: +; AVX1: # %bb.0: +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 +; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 +; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2 +; AVX1-NEXT: vpcmpgtq %xmm1, %xmm3, %xmm1 +; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2 +; AVX1-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm0 +; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: vmovmskps %ymm0, %eax +; AVX1-NEXT: movb %al, (%rdi) +; AVX1-NEXT: vzeroupper +; AVX1-NEXT: retq +; +; AVX2-LABEL: bitcast_8i64_store: +; AVX2: # %bb.0: +; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX2-NEXT: vpcmpgtq %ymm1, %ymm2, %ymm1 +; AVX2-NEXT: vpcmpgtq %ymm0, %ymm2, %ymm0 +; AVX2-NEXT: vpackssdw %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3] +; AVX2-NEXT: vmovmskps %ymm0, %eax +; AVX2-NEXT: movb %al, (%rdi) +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq +; +; AVX512F-LABEL: bitcast_8i64_store: +; AVX512F: # %bb.0: +; AVX512F-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512F-NEXT: vpcmpgtq %zmm0, %zmm1, %k0 +; AVX512F-NEXT: kmovw %k0, %eax +; AVX512F-NEXT: movb %al, (%rdi) +; AVX512F-NEXT: vzeroupper +; AVX512F-NEXT: retq +; +; AVX512BW-LABEL: bitcast_8i64_store: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512BW-NEXT: vpcmpgtq %zmm0, %zmm1, %k0 +; AVX512BW-NEXT: kmovd %k0, %eax +; AVX512BW-NEXT: movb %al, (%rdi) +; AVX512BW-NEXT: vzeroupper +; AVX512BW-NEXT: retq + %a1 = icmp slt <8 x i64> %a0, zeroinitializer + %a2 = bitcast <8 x i1> %a1 to i8 + store i8 %a2, i8* %p + ret void +}