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[RISCV] atomic_store_nn have a different layout to regular store 

We cannot directy reuse the patterns of StPat because for some reason the store
DAG node and the atomic_store_nn DAG nodes put the ptr and the value in
different positions. Currently we attempt to store the address to an address
formed by the value.

Differential Revision: https://reviews.llvm.org/D51217

llvm-svn: 340722
This commit is contained in:
Roger Ferrer Ibanez 2018-08-27 07:08:18 +00:00
parent be4a54940e
commit fe28217048
2 changed files with 27 additions and 16 deletions
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19
llvm/lib/Target/RISCV/RISCVInstrInfoA.td
View File

@ -44,6 +44,17 @@ multiclass AMO_rr_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr> {
def _AQ_RL : AMO_rr<funct5, 1, 1, funct3, opcodestr # ".aqrl">;
}
multiclass AtomicStPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy> {
def : Pat<(StoreOp GPR:$rs1, StTy:$rs2), (Inst StTy:$rs2, GPR:$rs1, 0)>;
def : Pat<(StoreOp AddrFI:$rs1, StTy:$rs2), (Inst StTy:$rs2, AddrFI:$rs1, 0)>;
def : Pat<(StoreOp (add GPR:$rs1, simm12:$imm12), StTy:$rs2),
(Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>;
def : Pat<(StoreOp (add AddrFI:$rs1, simm12:$imm12), StTy:$rs2),
(Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>;
def : Pat<(StoreOp (IsOrAdd AddrFI:$rs1, simm12:$imm12), StTy:$rs2),
(Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>;
}
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
@ -91,7 +102,7 @@ defm : LdPat<atomic_load_8, LB>;
defm : LdPat<atomic_load_16, LH>;
defm : LdPat<atomic_load_32, LW>;
defm : StPat<atomic_store_8, SB, GPR>;
defm : StPat<atomic_store_16, SH, GPR>;
defm : StPat<atomic_store_32, SW, GPR>;
} // Predicates = [HasStdExtF]
defm : AtomicStPat<atomic_store_8, SB, GPR>;
defm : AtomicStPat<atomic_store_16, SH, GPR>;
defm : AtomicStPat<atomic_store_32, SW, GPR>;
} // Predicates = [HasStdExtA]

24
llvm/test/CodeGen/RISCV/atomic-load-store.ll
View File

@ -350,7 +350,7 @@ define void @atomic_store_i8_unordered(i8 *%a, i8 %b) nounwind {
;
; RV32IA-LABEL: atomic_store_i8_unordered:
; RV32IA: # %bb.0:
; RV32IA-NEXT: sb a0, 0(a1)
; RV32IA-NEXT: sb a1, 0(a0)
; RV32IA-NEXT: ret
store atomic i8 %b, i8* %a unordered, align 1
ret void
@ -369,7 +369,7 @@ define void @atomic_store_i8_monotonic(i8 *%a, i8 %b) nounwind {
;
; RV32IA-LABEL: atomic_store_i8_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: sb a0, 0(a1)
; RV32IA-NEXT: sb a1, 0(a0)
; RV32IA-NEXT: ret
store atomic i8 %b, i8* %a monotonic, align 1
ret void
@ -389,7 +389,7 @@ define void @atomic_store_i8_release(i8 *%a, i8 %b) nounwind {
; RV32IA-LABEL: atomic_store_i8_release:
; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w
; RV32IA-NEXT: sb a0, 0(a1)
; RV32IA-NEXT: sb a1, 0(a0)
; RV32IA-NEXT: ret
store atomic i8 %b, i8* %a release, align 1
ret void
@ -409,7 +409,7 @@ define void @atomic_store_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32IA-LABEL: atomic_store_i8_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w
; RV32IA-NEXT: sb a0, 0(a1)
; RV32IA-NEXT: sb a1, 0(a0)
; RV32IA-NEXT: ret
store atomic i8 %b, i8* %a seq_cst, align 1
ret void
@ -428,7 +428,7 @@ define void @atomic_store_i16_unordered(i16 *%a, i16 %b) nounwind {
;
; RV32IA-LABEL: atomic_store_i16_unordered:
; RV32IA: # %bb.0:
; RV32IA-NEXT: sh a0, 0(a1)
; RV32IA-NEXT: sh a1, 0(a0)
; RV32IA-NEXT: ret
store atomic i16 %b, i16* %a unordered, align 2
ret void
@ -447,7 +447,7 @@ define void @atomic_store_i16_monotonic(i16 *%a, i16 %b) nounwind {
;
; RV32IA-LABEL: atomic_store_i16_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: sh a0, 0(a1)
; RV32IA-NEXT: sh a1, 0(a0)
; RV32IA-NEXT: ret
store atomic i16 %b, i16* %a monotonic, align 2
ret void
@ -467,7 +467,7 @@ define void @atomic_store_i16_release(i16 *%a, i16 %b) nounwind {
; RV32IA-LABEL: atomic_store_i16_release:
; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w
; RV32IA-NEXT: sh a0, 0(a1)
; RV32IA-NEXT: sh a1, 0(a0)
; RV32IA-NEXT: ret
store atomic i16 %b, i16* %a release, align 2
ret void
@ -487,7 +487,7 @@ define void @atomic_store_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32IA-LABEL: atomic_store_i16_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w
; RV32IA-NEXT: sh a0, 0(a1)
; RV32IA-NEXT: sh a1, 0(a0)
; RV32IA-NEXT: ret
store atomic i16 %b, i16* %a seq_cst, align 2
ret void
@ -506,7 +506,7 @@ define void @atomic_store_i32_unordered(i32 *%a, i32 %b) nounwind {
;
; RV32IA-LABEL: atomic_store_i32_unordered:
; RV32IA: # %bb.0:
; RV32IA-NEXT: sw a0, 0(a1)
; RV32IA-NEXT: sw a1, 0(a0)
; RV32IA-NEXT: ret
store atomic i32 %b, i32* %a unordered, align 4
ret void
@ -525,7 +525,7 @@ define void @atomic_store_i32_monotonic(i32 *%a, i32 %b) nounwind {
;
; RV32IA-LABEL: atomic_store_i32_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: sw a0, 0(a1)
; RV32IA-NEXT: sw a1, 0(a0)
; RV32IA-NEXT: ret
store atomic i32 %b, i32* %a monotonic, align 4
ret void
@ -545,7 +545,7 @@ define void @atomic_store_i32_release(i32 *%a, i32 %b) nounwind {
; RV32IA-LABEL: atomic_store_i32_release:
; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w
; RV32IA-NEXT: sw a0, 0(a1)
; RV32IA-NEXT: sw a1, 0(a0)
; RV32IA-NEXT: ret
store atomic i32 %b, i32* %a release, align 4
ret void
@ -565,7 +565,7 @@ define void @atomic_store_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32IA-LABEL: atomic_store_i32_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: fence rw, w
; RV32IA-NEXT: sw a0, 0(a1)
; RV32IA-NEXT: sw a1, 0(a0)
; RV32IA-NEXT: ret
store atomic i32 %b, i32* %a seq_cst, align 4
ret void