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[PowerPC] add RUN lines for both endians to test; NFC 

The load narrowing transform works for both targets,
so we might as well test both with simple examples
like this.
This commit is contained in:
Sanjay Patel 2022-01-13 10:45:31 -05:00
parent ccd7e7830f
commit fe17ce0fa6
1 changed files with 15 additions and 15 deletions
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30
llvm/test/CodeGen/PowerPC/lbz-from-ld-shift.ll
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@ -1,18 +1,18 @@
; RUN: llc -verify-machineinstrs -mcpu=ppc64 < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs -mtriple=powerpc64-- < %s | FileCheck %s --check-prefixes=BE
; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs -mtriple=powerpc64le-- < %s | FileCheck %s --check-prefixes=LE
; Function Attrs: nounwind readonly
define signext i32 @test(i32* nocapture readonly %P) #0 {
entry:
%0 = load i32, i32* %P, align 4
%shr = lshr i32 %0, 24
define signext i32 @test(i32* nocapture readonly %P) nounwind {
; BE-LABEL: test:
; BE: # %bb.0:
; BE-NEXT: lbz r3, 0(r3)
; BE-NEXT: blr
;
; LE-LABEL: test:
; LE: # %bb.0:
; LE-NEXT: lbz r3, 3(r3)
; LE-NEXT: blr
%t0 = load i32, i32* %P, align 4
%shr = lshr i32 %t0, 24
ret i32 %shr
; CHECK-LABEL: @test
; CHECK: lbz 3, 0(3)
; CHECK: blr
}
attributes #0 = { nounwind readonly }