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[DAGCombiner] Teach SimplifySetCC SETUGE X, SINTMIN -> SETLT X, 0 and SETULE X, SINTMAX -> SETGT X, -1. 

These aren't the canonical forms we'd get from InstCombine, but
we do have X86 tests for them. Recognizing them is pretty cheap.

While there make use of APInt:isSignedMinValue/isSignedMaxValue
instead of creating a new APInt to compare with. Also use
SelectionDAG::getAllOnesConstant helper to hide the all ones
APInt creation.
This commit is contained in:
Craig Topper 2020-08-08 22:09:21 -07:00
parent 95e61ed85c
commit fdfdee98ac
2 changed files with 10 additions and 14 deletions
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18
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -3901,20 +3901,20 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
// TODO: Support this for vectors after legalize ops. // TODO: Support this for vectors after legalize ops.
if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { if (!VT.isVector() || DCI.isBeforeLegalizeOps()) {
// SETUGT X, SINTMAX -> SETLT X, 0 // SETUGT X, SINTMAX -> SETLT X, 0
if (Cond == ISD::SETUGT && // SETUGE X, SINTMIN -> SETLT X, 0
C1 == APInt::getSignedMaxValue(OperandBitSize)) if ((Cond == ISD::SETUGT && C1.isMaxSignedValue()) ||
(Cond == ISD::SETUGE && C1.isMinSignedValue()))
return DAG.getSetCC(dl, VT, N0, return DAG.getSetCC(dl, VT, N0,
DAG.getConstant(0, dl, N1.getValueType()), DAG.getConstant(0, dl, N1.getValueType()),
ISD::SETLT); ISD::SETLT);
// SETULT X, SINTMIN -> SETGT X, -1 // SETULT X, SINTMIN -> SETGT X, -1
if (Cond == ISD::SETULT && // SETULE X, SINTMAX -> SETGT X, -1
C1 == APInt::getSignedMinValue(OperandBitSize)) { if ((Cond == ISD::SETULT && C1.isMinSignedValue()) ||
SDValue ConstMinusOne = (Cond == ISD::SETULE && C1.isMaxSignedValue()))
DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), dl, return DAG.getSetCC(dl, VT, N0,
N1.getValueType()); DAG.getAllOnesConstant(dl, N1.getValueType()),
return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); ISD::SETGT);
}
} }
} }

6
llvm/test/CodeGen/X86/vector-compare-simplify.ll
View File

@ -293,10 +293,8 @@ define <4 x i32> @ugt_smax(<4 x i32> %x) {
define <4 x i32> @ule_smax(<4 x i32> %x) { define <4 x i32> @ule_smax(<4 x i32> %x) {
; CHECK-LABEL: ule_smax: ; CHECK-LABEL: ule_smax:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: pxor {{.*}}(%rip), %xmm0
; CHECK-NEXT: pcmpeqd %xmm1, %xmm1 ; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
; CHECK-NEXT: pcmpgtd %xmm1, %xmm0 ; CHECK-NEXT: pcmpgtd %xmm1, %xmm0
; CHECK-NEXT: pxor %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%cmp = icmp ule <4 x i32> %x, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> %cmp = icmp ule <4 x i32> %x, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
%r = sext <4 x i1> %cmp to <4 x i32> %r = sext <4 x i1> %cmp to <4 x i32>
@ -317,11 +315,9 @@ define <4 x i32> @ult_smin(<4 x i32> %x) {
define <4 x i32> @uge_smin(<4 x i32> %x) { define <4 x i32> @uge_smin(<4 x i32> %x) {
; CHECK-LABEL: uge_smin: ; CHECK-LABEL: uge_smin:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: pxor {{.*}}(%rip), %xmm0
; CHECK-NEXT: pxor %xmm1, %xmm1 ; CHECK-NEXT: pxor %xmm1, %xmm1
; CHECK-NEXT: pcmpgtd %xmm0, %xmm1 ; CHECK-NEXT: pcmpgtd %xmm0, %xmm1
; CHECK-NEXT: pcmpeqd %xmm0, %xmm0 ; CHECK-NEXT: movdqa %xmm1, %xmm0
; CHECK-NEXT: pxor %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%cmp = icmp uge <4 x i32> %x, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> %cmp = icmp uge <4 x i32> %x, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
%r = sext <4 x i1> %cmp to <4 x i32> %r = sext <4 x i1> %cmp to <4 x i32>