From fdfdee98ac81dc7554bb2d7f5e99614e0086b4f0 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sat, 8 Aug 2020 22:09:21 -0700 Subject: [PATCH] [DAGCombiner] Teach SimplifySetCC SETUGE X, SINTMIN -> SETLT X, 0 and SETULE X, SINTMAX -> SETGT X, -1. These aren't the canonical forms we'd get from InstCombine, but we do have X86 tests for them. Recognizing them is pretty cheap. While there make use of APInt:isSignedMinValue/isSignedMaxValue instead of creating a new APInt to compare with. Also use SelectionDAG::getAllOnesConstant helper to hide the all ones APInt creation. --- .../CodeGen/SelectionDAG/TargetLowering.cpp | 18 +++++++++--------- .../CodeGen/X86/vector-compare-simplify.ll | 6 +----- 2 files changed, 10 insertions(+), 14 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 97b944455238..70cf4aafd870 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -3901,20 +3901,20 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, // TODO: Support this for vectors after legalize ops. if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { // SETUGT X, SINTMAX -> SETLT X, 0 - if (Cond == ISD::SETUGT && - C1 == APInt::getSignedMaxValue(OperandBitSize)) + // SETUGE X, SINTMIN -> SETLT X, 0 + if ((Cond == ISD::SETUGT && C1.isMaxSignedValue()) || + (Cond == ISD::SETUGE && C1.isMinSignedValue())) return DAG.getSetCC(dl, VT, N0, DAG.getConstant(0, dl, N1.getValueType()), ISD::SETLT); // SETULT X, SINTMIN -> SETGT X, -1 - if (Cond == ISD::SETULT && - C1 == APInt::getSignedMinValue(OperandBitSize)) { - SDValue ConstMinusOne = - DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), dl, - N1.getValueType()); - return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); - } + // SETULE X, SINTMAX -> SETGT X, -1 + if ((Cond == ISD::SETULT && C1.isMinSignedValue()) || + (Cond == ISD::SETULE && C1.isMaxSignedValue())) + return DAG.getSetCC(dl, VT, N0, + DAG.getAllOnesConstant(dl, N1.getValueType()), + ISD::SETGT); } } diff --git a/llvm/test/CodeGen/X86/vector-compare-simplify.ll b/llvm/test/CodeGen/X86/vector-compare-simplify.ll index 4eea1ea18c6c..289d7bde0935 100644 --- a/llvm/test/CodeGen/X86/vector-compare-simplify.ll +++ b/llvm/test/CodeGen/X86/vector-compare-simplify.ll @@ -293,10 +293,8 @@ define <4 x i32> @ugt_smax(<4 x i32> %x) { define <4 x i32> @ule_smax(<4 x i32> %x) { ; CHECK-LABEL: ule_smax: ; CHECK: # %bb.0: -; CHECK-NEXT: pxor {{.*}}(%rip), %xmm0 ; CHECK-NEXT: pcmpeqd %xmm1, %xmm1 ; CHECK-NEXT: pcmpgtd %xmm1, %xmm0 -; CHECK-NEXT: pxor %xmm1, %xmm0 ; CHECK-NEXT: retq %cmp = icmp ule <4 x i32> %x, %r = sext <4 x i1> %cmp to <4 x i32> @@ -317,11 +315,9 @@ define <4 x i32> @ult_smin(<4 x i32> %x) { define <4 x i32> @uge_smin(<4 x i32> %x) { ; CHECK-LABEL: uge_smin: ; CHECK: # %bb.0: -; CHECK-NEXT: pxor {{.*}}(%rip), %xmm0 ; CHECK-NEXT: pxor %xmm1, %xmm1 ; CHECK-NEXT: pcmpgtd %xmm0, %xmm1 -; CHECK-NEXT: pcmpeqd %xmm0, %xmm0 -; CHECK-NEXT: pxor %xmm1, %xmm0 +; CHECK-NEXT: movdqa %xmm1, %xmm0 ; CHECK-NEXT: retq %cmp = icmp uge <4 x i32> %x, %r = sext <4 x i1> %cmp to <4 x i32>