From fdf9bf4f16739daa62fa8d9177b1c3a8346728ae Mon Sep 17 00:00:00 2001 From: Justin Bogner Date: Tue, 10 Oct 2017 23:50:49 +0000 Subject: [PATCH] CodeGen: Minor cleanups to use MachineInstr::getMF. NFC Since r315388 we have a shorter way to say this, so we'll replace MI->getParent()->getParent() with MI->getMF() in a few places. llvm-svn: 315390 --- .../CodeGen/GlobalISel/InstructionSelectorImpl.h | 5 ++--- .../llvm/CodeGen/GlobalISel/MachineIRBuilder.h | 3 +-- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 4 ++-- llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp | 2 +- llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp | 10 +++++----- llvm/lib/CodeGen/IfConversion.cpp | 5 ++--- llvm/lib/CodeGen/LiveDebugValues.cpp | 4 ++-- llvm/lib/CodeGen/LocalStackSlotAllocation.cpp | 2 +- llvm/lib/CodeGen/MIRPrinter.cpp | 13 ++++++------- llvm/lib/CodeGen/MachineBasicBlock.cpp | 2 +- llvm/lib/CodeGen/MachineInstr.cpp | 10 +++++----- llvm/lib/CodeGen/MachineLICM.cpp | 6 +++--- llvm/lib/CodeGen/MachineOutliner.cpp | 3 +-- llvm/lib/CodeGen/MachinePipeliner.cpp | 2 +- llvm/lib/CodeGen/MachineScheduler.cpp | 2 +- llvm/lib/CodeGen/RegisterCoalescer.cpp | 2 +- llvm/lib/CodeGen/RegisterScavenging.cpp | 4 ++-- llvm/lib/CodeGen/TargetInstrInfo.cpp | 12 ++++++------ llvm/lib/CodeGen/TargetLoweringBase.cpp | 2 +- llvm/lib/CodeGen/TargetSchedule.cpp | 2 +- 20 files changed, 45 insertions(+), 50 deletions(-) diff --git a/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h b/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h index 109f1433db4e..a43c663bd6e5 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h @@ -310,9 +310,8 @@ bool InstructionSelector::executeMatchTable( int64_t NewOpcode = MatchTable[CurrentIdx++]; assert((size_t)NewInsnID == OutMIs.size() && "Expected to store MIs in order"); - OutMIs.push_back( - MachineInstrBuilder(*State.MIs[OldInsnID]->getParent()->getParent(), - State.MIs[OldInsnID])); + OutMIs.push_back(MachineInstrBuilder(*State.MIs[OldInsnID]->getMF(), + State.MIs[OldInsnID])); OutMIs[NewInsnID]->setDesc(TII.get(NewOpcode)); DEBUG(dbgs() << CurrentIdx << ": GIR_MutateOpcode(OutMIs[" << NewInsnID << "], MIs[" << OldInsnID << "], " << NewOpcode << ")\n"); diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h index 214314cdd8e4..5fe3137d6d70 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h @@ -93,8 +93,7 @@ public: /// Some constructors for easy use. MachineIRBuilder() = default; MachineIRBuilder(MachineFunction &MF) { setMF(MF); } - MachineIRBuilder(MachineInstr &MI) - : MachineIRBuilder(*MI.getParent()->getParent()) { + MachineIRBuilder(MachineInstr &MI) : MachineIRBuilder(*MI.getMF()) { setInstr(MI); } diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index 75de005bea17..b183dde4baf9 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -744,7 +744,7 @@ void AsmPrinter::EmitFunctionEntryLabel() { /// emitComments - Pretty-print comments for instructions. static void emitComments(const MachineInstr &MI, raw_ostream &CommentOS, AsmPrinter *AP) { - const MachineFunction *MF = MI.getParent()->getParent(); + const MachineFunction *MF = MI.getMF(); const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); // Check for spills and reloads @@ -2846,7 +2846,7 @@ void AsmPrinter::emitXRayTable() { void AsmPrinter::recordSled(MCSymbol *Sled, const MachineInstr &MI, SledKind Kind, uint8_t Version) { - auto Fn = MI.getParent()->getParent()->getFunction(); + auto Fn = MI.getMF()->getFunction(); auto Attr = Fn->getFnAttribute("function-instrument"); bool LogArgs = Fn->hasFnAttribute("xray-log-args"); bool AlwaysInstrument = diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp index 138028b768af..4844d68172be 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp @@ -1148,7 +1148,7 @@ void DwarfDebug::beginInstruction(const MachineInstr *MI) { DebugHandlerBase::beginInstruction(MI); assert(CurMI); - const auto *SP = MI->getParent()->getParent()->getFunction()->getSubprogram(); + const auto *SP = MI->getMF()->getFunction()->getSubprogram(); if (!SP || SP->getUnit()->getEmissionKind() == DICompileUnit::NoDebug) return; diff --git a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp index a841902feed1..632d9fd767cb 100644 --- a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp +++ b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp @@ -151,7 +151,7 @@ RegisterBankInfo::getInstrMappingImpl(const MachineInstr &MI) const { // is important. The rest is not constrained. unsigned NumOperandsForMapping = IsCopyLike ? 1 : MI.getNumOperands(); - const MachineFunction &MF = *MI.getParent()->getParent(); + const MachineFunction &MF = *MI.getMF(); const TargetSubtargetInfo &STI = MF.getSubtarget(); const TargetRegisterInfo &TRI = *STI.getRegisterInfo(); const MachineRegisterInfo &MRI = MF.getRegInfo(); @@ -543,9 +543,9 @@ bool RegisterBankInfo::InstructionMapping::verify( // For PHI, we only care about mapping the definition. assert(NumOperands == (isCopyLike(MI) ? 1 : MI.getNumOperands()) && "NumOperands must match, see constructor"); - assert(MI.getParent() && MI.getParent()->getParent() && + assert(MI.getParent() && MI.getMF() && "MI must be connected to a MachineFunction"); - const MachineFunction &MF = *MI.getParent()->getParent(); + const MachineFunction &MF = *MI.getMF(); (void)MF; for (unsigned Idx = 0; Idx < NumOperands; ++Idx) { @@ -725,8 +725,8 @@ void RegisterBankInfo::OperandsMapper::print(raw_ostream &OS, // If we have a function, we can pretty print the name of the registers. // Otherwise we will print the raw numbers. const TargetRegisterInfo *TRI = - getMI().getParent() && getMI().getParent()->getParent() - ? getMI().getParent()->getParent()->getSubtarget().getRegisterInfo() + getMI().getParent() && getMI().getMF() + ? getMI().getMF()->getSubtarget().getRegisterInfo() : nullptr; bool IsFirst = true; for (unsigned Idx = 0; Idx != NumOpds; ++Idx) { diff --git a/llvm/lib/CodeGen/IfConversion.cpp b/llvm/lib/CodeGen/IfConversion.cpp index ccb992d92e54..08720d1271f3 100644 --- a/llvm/lib/CodeGen/IfConversion.cpp +++ b/llvm/lib/CodeGen/IfConversion.cpp @@ -1361,8 +1361,7 @@ static void InsertUncondBranch(MachineBasicBlock &MBB, MachineBasicBlock &ToMBB, /// Behaves like LiveRegUnits::StepForward() but also adds implicit uses to all /// values defined in MI which are also live/used by MI. static void UpdatePredRedefs(MachineInstr &MI, LivePhysRegs &Redefs) { - const TargetRegisterInfo *TRI = MI.getParent()->getParent() - ->getSubtarget().getRegisterInfo(); + const TargetRegisterInfo *TRI = MI.getMF()->getSubtarget().getRegisterInfo(); // Before stepping forward past MI, remember which regs were live // before MI. This is needed to set the Undef flag only when reg is @@ -1382,7 +1381,7 @@ static void UpdatePredRedefs(MachineInstr &MI, LivePhysRegs &Redefs) { unsigned Reg = Clobber.first; MachineOperand &Op = const_cast(*Clobber.second); MachineInstr *OpMI = Op.getParent(); - MachineInstrBuilder MIB(*OpMI->getParent()->getParent(), OpMI); + MachineInstrBuilder MIB(*OpMI->getMF(), OpMI); if (Op.isRegMask()) { // First handle regmasks. They clobber any entries in the mask which // means that we need a def for those registers. diff --git a/llvm/lib/CodeGen/LiveDebugValues.cpp b/llvm/lib/CodeGen/LiveDebugValues.cpp index bca3361ad4cb..a45b1e39feed 100644 --- a/llvm/lib/CodeGen/LiveDebugValues.cpp +++ b/llvm/lib/CodeGen/LiveDebugValues.cpp @@ -374,7 +374,7 @@ void LiveDebugValues::transferDebugValue(const MachineInstr &MI, void LiveDebugValues::transferRegisterDef(MachineInstr &MI, OpenRangesSet &OpenRanges, const VarLocMap &VarLocIDs) { - MachineFunction *MF = MI.getParent()->getParent(); + MachineFunction *MF = MI.getMF(); const TargetLowering *TLI = MF->getSubtarget().getTargetLowering(); unsigned SP = TLI->getStackPointerRegisterToSaveRestore(); SparseBitVector<> KillSet; @@ -450,7 +450,7 @@ void LiveDebugValues::transferSpillInst(MachineInstr &MI, VarLocMap &VarLocIDs, SpillMap &Spills) { unsigned Reg; - MachineFunction *MF = MI.getParent()->getParent(); + MachineFunction *MF = MI.getMF(); if (!isSpillInstruction(MI, MF, Reg)) return; diff --git a/llvm/lib/CodeGen/LocalStackSlotAllocation.cpp b/llvm/lib/CodeGen/LocalStackSlotAllocation.cpp index 9d02422a09d6..2eab0376da2f 100644 --- a/llvm/lib/CodeGen/LocalStackSlotAllocation.cpp +++ b/llvm/lib/CodeGen/LocalStackSlotAllocation.cpp @@ -401,7 +401,7 @@ bool LocalStackSlotPass::insertFrameReferenceRegisters(MachineFunction &Fn) { continue; } - const MachineFunction *MF = MI.getParent()->getParent(); + const MachineFunction *MF = MI.getMF(); const TargetRegisterClass *RC = TRI->getPointerRegClass(*MF); BaseReg = Fn.getRegInfo().createVirtualRegister(RC); diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp index 74a4acf3c2d3..ae1bb36c6aac 100644 --- a/llvm/lib/CodeGen/MIRPrinter.cpp +++ b/llvm/lib/CodeGen/MIRPrinter.cpp @@ -703,7 +703,7 @@ static LLT getTypeToPrint(const MachineInstr &MI, unsigned OpIdx, } void MIPrinter::print(const MachineInstr &MI) { - const auto *MF = MI.getParent()->getParent(); + const auto *MF = MI.getMF(); const auto &MRI = MF->getRegInfo(); const auto &SubTarget = MF->getSubtarget(); const auto *TRI = SubTarget.getRegisterInfo(); @@ -854,8 +854,7 @@ static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) { void MIPrinter::printTargetFlags(const MachineOperand &Op) { if (!Op.getTargetFlags()) return; - const auto *TII = - Op.getParent()->getParent()->getParent()->getSubtarget().getInstrInfo(); + const auto *TII = Op.getParent()->getMF()->getSubtarget().getInstrInfo(); assert(TII && "expected instruction info"); auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags()); OS << "target-flags("; @@ -964,8 +963,8 @@ void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI, break; case MachineOperand::MO_TargetIndex: OS << "target-index("; - if (const auto *Name = getTargetIndexName( - *Op.getParent()->getParent()->getParent(), Op.getIndex())) + if (const auto *Name = + getTargetIndexName(*Op.getParent()->getMF(), Op.getIndex())) OS << Name; else OS << ""; @@ -1029,7 +1028,7 @@ void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI, OS << ""; break; case MachineOperand::MO_CFIIndex: { - const MachineFunction &MF = *Op.getParent()->getParent()->getParent(); + const MachineFunction &MF = *Op.getParent()->getMF(); print(MF.getFrameInstructions()[Op.getCFIIndex()], TRI); break; } @@ -1038,7 +1037,7 @@ void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI, if (ID < Intrinsic::num_intrinsics) OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')'; else { - const MachineFunction &MF = *Op.getParent()->getParent()->getParent(); + const MachineFunction &MF = *Op.getParent()->getMF(); const TargetIntrinsicInfo *TII = MF.getTarget().getIntrinsicInfo(); OS << "intrinsic(@" << TII->getName(ID) << ')'; } diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp index 81597afe6b02..d5758da0464c 100644 --- a/llvm/lib/CodeGen/MachineBasicBlock.cpp +++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp @@ -111,7 +111,7 @@ void ilist_traits::removeNodeFromList(MachineInstr *N) { assert(N->getParent() && "machine instruction not in a basic block"); // Remove from the use/def lists. - if (MachineFunction *MF = N->getParent()->getParent()) + if (MachineFunction *MF = N->getMF()) N->RemoveRegOperandsFromUseLists(MF->getRegInfo()); N->setParent(nullptr); diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp index fadade26a89a..ec2b09777742 100644 --- a/llvm/lib/CodeGen/MachineInstr.cpp +++ b/llvm/lib/CodeGen/MachineInstr.cpp @@ -311,7 +311,7 @@ bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { return true; // Calculate the size of the RegMask - const MachineFunction *MF = getParent()->getParent()->getParent(); + const MachineFunction *MF = getParent()->getMF(); const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32; @@ -1055,7 +1055,7 @@ MachineInstr::mergeMemRefsWith(const MachineInstr& Other) { if (CombinedNumMemRefs != uint8_t(CombinedNumMemRefs)) return std::make_pair(nullptr, 0); - MachineFunction *MF = getParent()->getParent(); + MachineFunction *MF = getMF(); mmo_iterator MemBegin = MF->allocateMemRefsArray(CombinedNumMemRefs); mmo_iterator MemEnd = std::copy(memoperands_begin(), memoperands_end(), MemBegin); @@ -1307,8 +1307,8 @@ MachineInstr::getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const { assert(getParent() && "Can't have an MBB reference here!"); - assert(getParent()->getParent() && "Can't have an MF reference here!"); - const MachineFunction &MF = *getParent()->getParent(); + assert(getMF() && "Can't have an MF reference here!"); + const MachineFunction &MF = *getMF(); // Most opcodes have fixed constraints in their MCInstrDesc. if (!isInlineAsm()) @@ -1669,7 +1669,7 @@ bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const { bool MachineInstr::mayAlias(AliasAnalysis *AA, MachineInstr &Other, bool UseTBAA) { - const MachineFunction *MF = getParent()->getParent(); + const MachineFunction *MF = getMF(); const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); const MachineFrameInfo &MFI = MF->getFrameInfo(); diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp index f83248d1ebf5..efb5c3371de2 100644 --- a/llvm/lib/CodeGen/MachineLICM.cpp +++ b/llvm/lib/CodeGen/MachineLICM.cpp @@ -917,8 +917,8 @@ bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) { // However, if the physreg is known to always be caller saved/restored // then this use is safe to hoist. if (!MRI->isConstantPhysReg(Reg) && - !(TRI->isCallerPreservedPhysReg(Reg, *I.getParent()->getParent()))) - return false; + !(TRI->isCallerPreservedPhysReg(Reg, *I.getMF()))) + return false; // Otherwise it's safe to move. continue; } else if (!MO.isDead()) { @@ -1191,7 +1191,7 @@ MachineInstr *MachineLICM::ExtractHoistableLoad(MachineInstr *MI) { &LoadRegIndex); if (NewOpc == 0) return nullptr; const MCInstrDesc &MID = TII->get(NewOpc); - MachineFunction &MF = *MI->getParent()->getParent(); + MachineFunction &MF = *MI->getMF(); const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI, MF); // Ok, we're unfolding. Create a temporary register and do the unfold. unsigned Reg = MRI->createVirtualRegister(RC); diff --git a/llvm/lib/CodeGen/MachineOutliner.cpp b/llvm/lib/CodeGen/MachineOutliner.cpp index 8e6e0b12409e..ef9eb55f6224 100644 --- a/llvm/lib/CodeGen/MachineOutliner.cpp +++ b/llvm/lib/CodeGen/MachineOutliner.cpp @@ -939,8 +939,7 @@ MachineOutliner::findCandidates(SuffixTree &ST, const TargetInstrInfo &TII, // Emit a remark explaining why we didn't outline this candidate. std::pair C = RepeatedSequenceLocs[0]; - MachineOptimizationRemarkEmitter MORE( - *(C.first->getParent()->getParent()), nullptr); + MachineOptimizationRemarkEmitter MORE(*(C.first->getMF()), nullptr); MachineOptimizationRemarkMissed R(DEBUG_TYPE, "NotOutliningCheaper", C.first->getDebugLoc(), C.first->getParent()); diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp index 91e1257ba4dd..d0616fd678bd 100644 --- a/llvm/lib/CodeGen/MachinePipeliner.cpp +++ b/llvm/lib/CodeGen/MachinePipeliner.cpp @@ -3353,7 +3353,7 @@ bool SwingSchedulerDAG::canUseLastOffsetValue(MachineInstr *MI, unsigned BaseReg = MI->getOperand(BasePosLd).getReg(); // Look for the Phi instruction. - MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); + MachineRegisterInfo &MRI = MI->getMF()->getRegInfo(); MachineInstr *Phi = MRI.getVRegDef(BaseReg); if (!Phi || !Phi->isPHI()) return false; diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index 9a86d0850b3e..674e83cf8082 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -2653,7 +2653,7 @@ void GenericScheduler::initialize(ScheduleDAGMI *dag) { void GenericScheduler::initPolicy(MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, unsigned NumRegionInstrs) { - const MachineFunction &MF = *Begin->getParent()->getParent(); + const MachineFunction &MF = *Begin->getMF(); const TargetLowering *TLI = MF.getSubtarget().getTargetLowering(); // Avoid setting up the register pressure tracker for small regions to save diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp index 152149ac9a79..30b2686d6208 100644 --- a/llvm/lib/CodeGen/RegisterCoalescer.cpp +++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp @@ -363,7 +363,7 @@ bool CoalescerPair::setRegisters(const MachineInstr *MI) { Flipped = true; } - const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); + const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo(); if (TargetRegisterInfo::isPhysicalRegister(Dst)) { // Eliminate DstSub on a physreg. diff --git a/llvm/lib/CodeGen/RegisterScavenging.cpp b/llvm/lib/CodeGen/RegisterScavenging.cpp index fdd10edf07f0..844ddb9ed3ff 100644 --- a/llvm/lib/CodeGen/RegisterScavenging.cpp +++ b/llvm/lib/CodeGen/RegisterScavenging.cpp @@ -463,7 +463,7 @@ RegScavenger::spill(unsigned Reg, const TargetRegisterClass &RC, int SPAdj, MachineBasicBlock::iterator &UseMI) { // Find an available scavenging slot with size and alignment matching // the requirements of the class RC. - const MachineFunction &MF = *Before->getParent()->getParent(); + const MachineFunction &MF = *Before->getMF(); const MachineFrameInfo &MFI = MF.getFrameInfo(); unsigned NeedSize = TRI->getSpillSize(RC); unsigned NeedAlign = TRI->getSpillAlignment(RC); @@ -536,7 +536,7 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC, MachineBasicBlock::iterator I, int SPAdj) { MachineInstr &MI = *I; - const MachineFunction &MF = *MI.getParent()->getParent(); + const MachineFunction &MF = *MI.getMF(); // Consider all allocatable registers in the register class initially BitVector Candidates = TRI->getAllocatableSet(MF, RC); diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp index 1b414c1f34e2..bac12efd6395 100644 --- a/llvm/lib/CodeGen/TargetInstrInfo.cpp +++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp @@ -191,7 +191,7 @@ MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr &MI, MachineInstr *CommutedMI = nullptr; if (NewMI) { // Create a new instruction. - MachineFunction &MF = *MI.getParent()->getParent(); + MachineFunction &MF = *MI.getMF(); CommutedMI = MF.CloneMachineInstr(&MI); } else { CommutedMI = &MI; @@ -438,7 +438,7 @@ static const TargetRegisterClass *canFoldCopy(const MachineInstr &MI, assert(TargetRegisterInfo::isVirtualRegister(FoldReg) && "Cannot fold physregs"); - const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); + const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo(); const TargetRegisterClass *RC = MRI.getRegClass(FoldReg); if (TargetRegisterInfo::isPhysicalRegister(LiveOp.getReg())) @@ -763,7 +763,7 @@ void TargetInstrInfo::reassociateOps( SmallVectorImpl &InsInstrs, SmallVectorImpl &DelInstrs, DenseMap &InstrIdxForVirtReg) const { - MachineFunction *MF = Root.getParent()->getParent(); + MachineFunction *MF = Root.getMF(); MachineRegisterInfo &MRI = MF->getRegInfo(); const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); @@ -846,7 +846,7 @@ void TargetInstrInfo::genAlternativeCodeSequence( SmallVectorImpl &InsInstrs, SmallVectorImpl &DelInstrs, DenseMap &InstIdxForVirtReg) const { - MachineRegisterInfo &MRI = Root.getParent()->getParent()->getRegInfo(); + MachineRegisterInfo &MRI = Root.getMF()->getRegInfo(); // Select the previous instruction in the sequence based on the input pattern. MachineInstr *Prev = nullptr; @@ -870,7 +870,7 @@ void TargetInstrInfo::genAlternativeCodeSequence( bool TargetInstrInfo::isReallyTriviallyReMaterializableGeneric( const MachineInstr &MI, AliasAnalysis *AA) const { - const MachineFunction &MF = *MI.getParent()->getParent(); + const MachineFunction &MF = *MI.getMF(); const MachineRegisterInfo &MRI = MF.getRegInfo(); // Remat clients assume operand 0 is the defined register. @@ -948,7 +948,7 @@ bool TargetInstrInfo::isReallyTriviallyReMaterializableGeneric( } int TargetInstrInfo::getSPAdjust(const MachineInstr &MI) const { - const MachineFunction *MF = MI.getParent()->getParent(); + const MachineFunction *MF = MI.getMF(); const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering(); bool StackGrowsDown = TFI->getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown; diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp index ea655e1faacf..ec971e147ebd 100644 --- a/llvm/lib/CodeGen/TargetLoweringBase.cpp +++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp @@ -866,7 +866,7 @@ MachineBasicBlock * TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI, MachineBasicBlock *MBB) const { MachineInstr *MI = &InitialMI; - MachineFunction &MF = *MI->getParent()->getParent(); + MachineFunction &MF = *MI->getMF(); MachineFrameInfo &MFI = MF.getFrameInfo(); // We're handling multiple types of operands here: diff --git a/llvm/lib/CodeGen/TargetSchedule.cpp b/llvm/lib/CodeGen/TargetSchedule.cpp index e1f7edc627b2..e1db9157f901 100644 --- a/llvm/lib/CodeGen/TargetSchedule.cpp +++ b/llvm/lib/CodeGen/TargetSchedule.cpp @@ -316,7 +316,7 @@ computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx, // correctly append imp-use operands, and readsReg() strangely returns false // for predicated defs. unsigned Reg = DefMI->getOperand(DefOperIdx).getReg(); - const MachineFunction &MF = *DefMI->getParent()->getParent(); + const MachineFunction &MF = *DefMI->getMF(); const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(*DepMI)) return computeInstrLatency(DefMI);