forked from OSchip/llvm-project
[ScalarizeMaskedMemIntrin] Fix the alignment calculation for the scalar stores of a masked store expansion.
It should be the minimum of the original alignment and the scalar size. llvm-svn: 343284
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@ -276,7 +276,7 @@ static void scalarizeMaskedStore(CallInst *CI) {
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}
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// Adjust alignment for the scalar instruction.
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AlignVal = std::max(AlignVal, EltTy->getPrimitiveSizeInBits() / 8);
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AlignVal = std::min(AlignVal, EltTy->getPrimitiveSizeInBits() / 8);
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// Bitcast %addr fron i8* to EltTy*
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Type *NewPtrType =
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EltTy->getPointerTo(cast<PointerType>(Ptr->getType())->getAddressSpace());
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@ -9,7 +9,7 @@ define void @scalarize_v2i64(<2 x i64>* %p, <2 x i1> %mask, <2 x i64> %data) {
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; CHECK: cond.store:
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; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i64> [[DATA:%.*]], i32 0
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; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, i64* [[TMP1]], i32 0
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; CHECK-NEXT: store i64 [[TMP3]], i64* [[TMP4]], align 128
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; CHECK-NEXT: store i64 [[TMP3]], i64* [[TMP4]], align 8
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; CHECK-NEXT: br label [[ELSE]]
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; CHECK: else:
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; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i1> [[MASK]], i32 1
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@ -17,7 +17,7 @@ define void @scalarize_v2i64(<2 x i64>* %p, <2 x i1> %mask, <2 x i64> %data) {
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; CHECK: cond.store1:
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; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i64> [[DATA]], i32 1
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; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, i64* [[TMP1]], i32 1
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; CHECK-NEXT: store i64 [[TMP6]], i64* [[TMP7]], align 128
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; CHECK-NEXT: store i64 [[TMP6]], i64* [[TMP7]], align 8
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; CHECK-NEXT: br label [[ELSE2]]
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; CHECK: else2:
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; CHECK-NEXT: ret void
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