forked from OSchip/llvm-project
[AMDGPU] Use SDWA for 16 bit subreg copy
This simplifies the logic and allows to use it on GFX8. Differential Revision: https://reviews.llvm.org/D78150
This commit is contained in:
Stanislav Mekhanoshin
parent
fc4e954ed5
commit
fde2aefa22
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@ -683,16 +683,6 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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assert(AMDGPU::VGPR_LO16RegClass.contains(SrcReg) ||
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AMDGPU::VGPR_HI16RegClass.contains(SrcReg));
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// d s
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// l -> l : hhhhxxxx : xxxxllll -> v_alignbyte_b32 d, s, d, 2
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// llllhhhh : xxxxllll -> v_alignbyte_b32 d, d, d, 2
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// l -> h : xxxxllll : xxxxhhhh -> v_lshlrev_b32 d, 16, d
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// llll0000 : xxxxhhhh -> v_alignbyte_b32 d, s, d, 2
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// h -> l : hhhhxxxx : llllxxxx -> v_lshrrev_b32 d, 16, d
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// 0000hhhh : llllxxxx -> v_alignbyte_b32 d, d, s, 2
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// h -> h : xxxxllll : hhhhxxxx -> v_alignbyte_b32 d, d, s, 2
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// llllhhhh : hhhhxxxx -> v_alignbyte_b32 d, d, d, 2
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bool DstLow = RC == &AMDGPU::VGPR_LO16RegClass;
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bool SrcLow = AMDGPU::VGPR_LO16RegClass.contains(SrcReg);
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DestReg = RI.getMatchingSuperReg(DestReg,
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@ -702,49 +692,18 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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SrcLow ? AMDGPU::lo16 : AMDGPU::hi16,
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&AMDGPU::VGPR_32RegClass);
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if (DestReg == SrcReg) {
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// l -> h : v_pk_add_u16 v1, v1, 0 op_sel_hi:[0,0]
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// h -> l : v_pk_add_u16 v1, v1, 0 op_sel:[1,0] op_sel_hi:[1,0]
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if (DstLow == SrcLow)
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return;
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BuildMI(MBB, MI, DL, get(AMDGPU::V_PK_ADD_U16), DestReg)
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.addImm(DstLow ? SISrcMods::OP_SEL_0 | SISrcMods::OP_SEL_1 : 0)
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.addReg(DestReg, RegState::Undef)
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.addImm(0) // src1_mod
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.addImm(0) // src1
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.addImm(0)
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.addImm(0)
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.addImm(0)
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.addImm(0)
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.addImm(0);
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return;
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}
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// Last instruction first:
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auto Last = BuildMI(MBB, MI, DL, get(AMDGPU::V_ALIGNBYTE_B32), DestReg)
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.addReg((SrcLow && !DstLow) ? SrcReg : DestReg,
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(SrcLow && !DstLow) ? getKillRegState(KillSrc) : 0)
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.addReg((!SrcLow && DstLow) ? SrcReg : DestReg,
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(!SrcLow && DstLow) ? getKillRegState(KillSrc) : 0)
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.addImm(2);
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unsigned OpcFirst = (DstLow == SrcLow) ? AMDGPU::V_ALIGNBYTE_B32
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: SrcLow ? AMDGPU::V_LSHRREV_B32_e32
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: AMDGPU::V_LSHLREV_B32_e32;
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auto First = BuildMI(MBB, &*Last, DL, get(OpcFirst), DestReg);
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if (DstLow == SrcLow) { // alignbyte
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First
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.addReg(SrcLow ? SrcReg : DestReg,
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SrcLow ? getKillRegState(KillSrc) : unsigned(RegState::Undef))
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.addReg(SrcLow ? DestReg : SrcReg,
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SrcLow ? unsigned(RegState::Undef) : getKillRegState(KillSrc))
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.addImm(2);
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} else {
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First.addImm(16)
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.addReg(DestReg, RegState::Undef);
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}
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auto MIB = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_sdwa), DestReg)
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.addImm(0) // src0_modifiers
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.addReg(SrcReg)
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.addImm(0) // clamp
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.addImm(DstLow ? AMDGPU::SDWA::SdwaSel::WORD_0
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: AMDGPU::SDWA::SdwaSel::WORD_1)
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.addImm(AMDGPU::SDWA::DstUnused::UNUSED_PRESERVE)
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.addImm(SrcLow ? AMDGPU::SDWA::SdwaSel::WORD_0
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: AMDGPU::SDWA::SdwaSel::WORD_1)
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.addReg(DestReg, RegState::Implicit | RegState::Undef);
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// First implicit operand is $exec.
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MIB->tieOperands(0, MIB->getNumOperands() - 1);
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return;
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}
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@ -1,8 +1,9 @@
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# RUN: llc -march=amdgcn -mcpu=gfx802 -start-before postrapseudos -asm-verbose=0 -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
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# RUN: llc -march=amdgcn -mcpu=gfx900 -start-before postrapseudos -asm-verbose=0 -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
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# RUN: llc -march=amdgcn -mcpu=gfx1010 -start-before postrapseudos -asm-verbose=0 -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,GFX10 %s
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# GCN-LABEL: {{^}}lo_to_lo:
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# GCN: v_alignbyte_b32 v1, v0, v1, 2
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# GCN-NEXT: v_alignbyte_b32 v1, v1, v1, 2
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# GCN: v_mov_b32_sdwa v1, v0 dst_sel:WORD_0 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0
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name: lo_to_lo
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tracksRegLiveness: true
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body: |
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@ -13,8 +14,7 @@ body: |
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...
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# GCN-LABEL: {{^}}lo_to_hi:
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# GCN: v_lshrrev_b32_e32 v1, 16, v1
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# GCN-NEXT: v_alignbyte_b32 v1, v0, v1, 2
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# GCN: v_mov_b32_sdwa v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0
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name: lo_to_hi
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tracksRegLiveness: true
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body: |
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@ -25,8 +25,7 @@ body: |
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...
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# GCN-LABEL: {{^}}hi_to_lo:
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# GCN: v_lshlrev_b32_e32 v1, 16, v1
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# GCN-NEXT: v_alignbyte_b32 v1, v1, v0, 2
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# GCN: v_mov_b32_sdwa v1, v0 dst_sel:WORD_0 dst_unused:UNUSED_PRESERVE src0_sel:WORD_1
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name: hi_to_lo
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tracksRegLiveness: true
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body: |
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@ -37,8 +36,7 @@ body: |
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...
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# GCN-LABEL: {{^}}hi_to_hi:
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# GCN: v_alignbyte_b32 v1, v1, v0, 2
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# GCN-NEXT: v_alignbyte_b32 v1, v1, v1, 2
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# GCN: v_mov_b32_sdwa v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_1
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name: hi_to_hi
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tracksRegLiveness: true
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body: |
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@ -50,6 +48,7 @@ body: |
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# GCN-LABEL: {{^}}lo_to_lo_samereg:
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# GCN: s_waitcnt
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# GFX10-NEXT: s_waitcnt_vscnt
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# GCN-NEXT: s_endpgm
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name: lo_to_lo_samereg
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tracksRegLiveness: true
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@ -61,7 +60,7 @@ body: |
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...
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# GCN-LABEL: {{^}}lo_to_hi_samereg:
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# GCN: v_pk_add_u16 v0, v0, 0 op_sel_hi:[0,0]
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# GCN: v_mov_b32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0
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name: lo_to_hi_samereg
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tracksRegLiveness: true
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body: |
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@ -72,7 +71,7 @@ body: |
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...
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# GCN-LABEL: {{^}}hi_to_lo_samereg:
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# GCN: v_pk_add_u16 v0, v0, 0 op_sel:[1,0] op_sel_hi:[1,0]
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# GCN: v_mov_b32_sdwa v0, v0 dst_sel:WORD_0 dst_unused:UNUSED_PRESERVE src0_sel:WORD_1
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name: hi_to_lo_samereg
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tracksRegLiveness: true
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body: |
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@ -84,6 +83,7 @@ body: |
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# GCN-LABEL: {{^}}hi_to_hi_samereg:
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# GCN: s_waitcnt
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# GFX10-NEXT: s_waitcnt_vscnt
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# GCN-NEXT: s_endpgm
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name: hi_to_hi_samereg
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tracksRegLiveness: true
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@ -95,8 +95,7 @@ body: |
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...
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# GCN-LABEL: {{^}}lo_to_lo_def_livein:
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# GCN: v_alignbyte_b32 v1, v0, v1, 2
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# GCN-NEXT: v_alignbyte_b32 v1, v1, v1, 2
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# GCN: v_mov_b32_sdwa v1, v0 dst_sel:WORD_0 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0
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name: lo_to_lo_def_livein
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tracksRegLiveness: true
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body: |
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@ -109,8 +108,7 @@ body: |
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...
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# GCN-LABEL: {{^}}lo_to_hi_def_livein:
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# GCN: v_lshrrev_b32_e32 v1, 16, v1
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# GCN-NEXT: v_alignbyte_b32 v1, v0, v1, 2
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# GCN: v_mov_b32_sdwa v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0
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name: lo_to_hi_def_livein
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tracksRegLiveness: true
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body: |
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@ -123,8 +121,7 @@ body: |
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...
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# GCN-LABEL: {{^}}hi_to_lo_def_livein:
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# GCN: v_lshlrev_b32_e32 v1, 16, v1
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# GCN-NEXT: v_alignbyte_b32 v1, v1, v0, 2
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# GCN: v_mov_b32_sdwa v1, v0 dst_sel:WORD_0 dst_unused:UNUSED_PRESERVE src0_sel:WORD_1
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name: hi_to_lo_def_livein
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tracksRegLiveness: true
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body: |
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@ -137,8 +134,7 @@ body: |
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...
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# GCN-LABEL: {{^}}hi_to_hi_def_livein:
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# GCN: v_alignbyte_b32 v1, v1, v0, 2
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# GCN-NEXT: v_alignbyte_b32 v1, v1, v1, 2
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# GCN: v_mov_b32_sdwa v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_1
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name: hi_to_hi_def_livein
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tracksRegLiveness: true
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body: |
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@ -152,10 +148,8 @@ body: |
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# TODO: This can be coalesced into a VGPR_32 copy
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# GCN-LABEL: {{^}}lo_to_lo_hi_to_hi:
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# GCN: v_alignbyte_b32 v1, v0, v1, 2
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# GCN-NEXT: v_alignbyte_b32 v1, v1, v1, 2
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# GCN-NEXT: v_alignbyte_b32 v1, v1, v0, 2
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# GCN-NEXT: v_alignbyte_b32 v1, v1, v1, 2
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# GCN: v_mov_b32_sdwa v1, v0 dst_sel:WORD_0 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0
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# GCN-NEXT: v_mov_b32_sdwa v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_1
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# GCN-NEXT: v_mov_b32_e32 v2, v1
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# GCN-NEXT: s_endpgm
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name: lo_to_lo_hi_to_hi
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@ -170,10 +164,8 @@ body: |
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...
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# GCN-LABEL: {{^}}lo_to_hi_hi_to_lo:
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# GCN: v_lshlrev_b32_e32 v1, 16, v1
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# GCN-NEXT: v_alignbyte_b32 v1, v1, v0, 2
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# GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1
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# GCN-NEXT: v_alignbyte_b32 v1, v0, v1, 2
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# GCN: v_mov_b32_sdwa v1, v0 dst_sel:WORD_0 dst_unused:UNUSED_PRESERVE src0_sel:WORD_1
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# GCN-NEXT: v_mov_b32_sdwa v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0
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# GCN-NEXT: v_mov_b32_e32 v2, v1
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# GCN-NEXT: s_endpgm
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name: lo_to_hi_hi_to_lo
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@ -190,6 +182,7 @@ body: |
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# NB: copy of undef just killed instead of expansion
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# GCN-LABEL: {{^}}lo_to_lo_undef:
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# GCN: s_waitcnt
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# GFX10-NEXT: s_waitcnt_vscnt
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# GCN-NEXT: v_mov_b32_e32 v2, v1
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# GCN-NEXT: s_endpgm
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name: lo_to_lo_undef
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