forked from OSchip/llvm-project
Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gates
codegen using the patterns; the latter gates the assembler recognizing the instruction. llvm-svn: 117931
This commit is contained in:
Jim Grosbach
parent
13ddd6d410
commit
fddf36d254
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@ -1147,7 +1147,7 @@ class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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let InOperandList = iops;
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let AsmString = asm;
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let Pattern = pattern;
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list<Predicate> Predicates = [IsThumb1Only];
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list<Predicate> Predicates = [IsThumb, IsThumb1Only];
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}
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class T1I<dag oops, dag iops, InstrItinClass itin,
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@ -1175,7 +1175,7 @@ class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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let InOperandList = !con(iops, (ins pred:$p));
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let AsmString = !strconcat(opc, "${s}${p}", asm);
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let Pattern = pattern;
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list<Predicate> Predicates = [IsThumb1Only];
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list<Predicate> Predicates = [IsThumb, IsThumb1Only];
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}
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class T1sI<dag oops, dag iops, InstrItinClass itin,
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@ -1197,7 +1197,7 @@ class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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let InOperandList = !con(iops, (ins pred:$p));
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let AsmString = !strconcat(opc, "${p}", asm);
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let Pattern = pattern;
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list<Predicate> Predicates = [IsThumb1Only];
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list<Predicate> Predicates = [IsThumb, IsThumb1Only];
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}
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class T1pI<dag oops, dag iops, InstrItinClass itin,
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@ -1316,7 +1316,7 @@ class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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let InOperandList = iops;
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let AsmString = asm;
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let Pattern = pattern;
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list<Predicate> Predicates = [IsThumb1Only];
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list<Predicate> Predicates = [IsThumb, IsThumb1Only];
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}
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class T2I<dag oops, dag iops, InstrItinClass itin,
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@ -1405,12 +1405,12 @@ class T2I_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, dag iops,
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// Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
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class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
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list<Predicate> Predicates = [IsThumb1Only, HasV5T];
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list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T];
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}
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// T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
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class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
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list<Predicate> Predicates = [IsThumb1Only];
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list<Predicate> Predicates = [IsThumb, IsThumb1Only];
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}
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// T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
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@ -127,11 +127,13 @@ def t_addrmode_sp : Operand<i32>,
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let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
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def tADJCALLSTACKUP :
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PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary, "",
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[(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb1Only]>;
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[(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
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Requires<[IsThumb, IsThumb1Only]>;
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def tADJCALLSTACKDOWN :
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PseudoInst<(outs), (ins i32imm:$amt), NoItinerary, "",
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[(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb1Only]>;
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[(ARMcallseq_start imm:$amt)]>,
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Requires<[IsThumb, IsThumb1Only]>;
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}
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def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
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@ -316,7 +318,7 @@ let isCall = 1,
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(outs), (ins tGPR:$func, variable_ops), IIC_Br,
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"mov\tlr, pc\n\tbx\t$func",
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[(ARMcall_nolink tGPR:$func)]>,
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Requires<[IsThumb1Only, IsNotDarwin]>;
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Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
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}
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// On Darwin R9 is call-clobbered.
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@ -352,7 +354,7 @@ let isCall = 1,
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(outs), (ins tGPR:$func, variable_ops), IIC_Br,
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"mov\tlr, pc\n\tbx\t$func",
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[(ARMcall_nolink tGPR:$func)]>,
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Requires<[IsThumb1Only, IsDarwin]>;
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Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
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}
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let isBranch = 1, isTerminator = 1 in {
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@ -764,7 +766,7 @@ def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr,
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def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
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"rev", "\t$dst, $src",
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[(set tGPR:$dst, (bswap tGPR:$src))]>,
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Requires<[IsThumb1Only, HasV6]>,
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Requires<[IsThumb, IsThumb1Only, HasV6]>,
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T1Misc<{1,0,1,0,0,0,?}>;
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def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
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@ -774,7 +776,7 @@ def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
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(or (and (shl tGPR:$src, (i32 8)), 0xFF00),
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(or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
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(and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
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Requires<[IsThumb1Only, HasV6]>,
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Requires<[IsThumb, IsThumb1Only, HasV6]>,
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T1Misc<{1,0,1,0,0,1,?}>;
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def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
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@ -783,7 +785,7 @@ def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
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(sext_inreg
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(or (srl (and tGPR:$src, 0xFF00), (i32 8)),
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(shl tGPR:$src, (i32 8))), i16))]>,
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Requires<[IsThumb1Only, HasV6]>,
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Requires<[IsThumb, IsThumb1Only, HasV6]>,
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T1Misc<{1,0,1,0,1,1,?}>;
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// rotate right register
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@ -828,14 +830,14 @@ def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
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def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
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"sxtb", "\t$dst, $src",
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[(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
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Requires<[IsThumb1Only, HasV6]>,
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Requires<[IsThumb, IsThumb1Only, HasV6]>,
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T1Misc<{0,0,1,0,0,1,?}>;
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// sign-extend short
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def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
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"sxth", "\t$dst, $src",
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[(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
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Requires<[IsThumb1Only, HasV6]>,
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Requires<[IsThumb, IsThumb1Only, HasV6]>,
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T1Misc<{0,0,1,0,0,0,?}>;
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// test
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@ -849,14 +851,14 @@ def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iTSTr,
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def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
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"uxtb", "\t$dst, $src",
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[(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
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Requires<[IsThumb1Only, HasV6]>,
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Requires<[IsThumb, IsThumb1Only, HasV6]>,
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T1Misc<{0,0,1,0,1,1,?}>;
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// zero-extend short
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def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
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"uxth", "\t$dst, $src",
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[(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
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Requires<[IsThumb1Only, HasV6]>,
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Requires<[IsThumb, IsThumb1Only, HasV6]>,
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T1Misc<{0,0,1,0,1,0,?}>;
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@ -994,10 +996,10 @@ def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
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// ldr{b|h} + sxt{b|h} instead.
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def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
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(tSXTB (tLDRB t_addrmode_s1:$addr))>,
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Requires<[IsThumb1Only, HasV6]>;
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Requires<[IsThumb, IsThumb1Only, HasV6]>;
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def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
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(tSXTH (tLDRH t_addrmode_s2:$addr))>,
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Requires<[IsThumb1Only, HasV6]>;
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Requires<[IsThumb, IsThumb1Only, HasV6]>;
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def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
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(tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>;
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@ -1022,4 +1024,4 @@ def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
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NoItinerary, "",
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[(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
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imm:$cp))]>,
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Requires<[IsThumb1Only]>;
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Requires<[IsThumb, IsThumb1Only]>;
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