forked from OSchip/llvm-project
[AArch64] Attempt to emitConjunction from brcond
We currently use emitConjunction to create CCMP conjunctions from the conditions of selects, helping turning and/ors into more optimal ccmp sequences that don't need to go through csels. This extends that to also be used whilst lowering brcond, giving more opportunity for better condition generation. Differential Revision: https://reviews.llvm.org/D118650
This commit is contained in:
David Green
parent
c00db97159
commit
fdce239ae9
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@ -345,7 +345,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Custom);
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setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
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setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
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setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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setOperationAction(ISD::BRCOND, MVT::Other, Custom);
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setOperationAction(ISD::BR_CC, MVT::i32, Custom);
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setOperationAction(ISD::BR_CC, MVT::i64, Custom);
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setOperationAction(ISD::BR_CC, MVT::f16, Custom);
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@ -5004,6 +5004,22 @@ SDValue AArch64TargetLowering::LowerABS(SDValue Op, SelectionDAG &DAG) const {
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Cmp.getValue(1));
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}
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static SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
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SDValue Chain = Op.getOperand(0);
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SDValue Cond = Op.getOperand(1);
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SDValue Dest = Op.getOperand(2);
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AArch64CC::CondCode CC;
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if (SDValue Cmp = emitConjunction(DAG, Cond, CC)) {
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SDLoc dl(Op);
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SDValue CCVal = DAG.getConstant(CC, dl, MVT::i32);
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return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
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Cmp);
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}
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return SDValue();
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}
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SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
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SelectionDAG &DAG) const {
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LLVM_DEBUG(dbgs() << "Custom lowering: ");
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@ -5023,6 +5039,8 @@ SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
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case ISD::STRICT_FSETCC:
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case ISD::STRICT_FSETCCS:
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return LowerSETCC(Op, DAG);
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case ISD::BRCOND:
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return LowerBRCOND(Op, DAG);
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case ISD::BR_CC:
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return LowerBR_CC(Op, DAG);
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case ISD::SELECT:
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@ -6,19 +6,17 @@ declare void @dummy()
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define i32 @and_eq_ne_ult(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
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; CHECK-LABEL: and_eq_ne_ult:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w0, w1
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; CHECK-NEXT: ccmp w2, w3, #4, eq
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; CHECK-NEXT: b.ne .LBB0_3
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; CHECK-NEXT: // %bb.1: // %entry
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; CHECK-NEXT: cmp w4, w5
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; CHECK-NEXT: b.lo .LBB0_3
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; CHECK-NEXT: // %bb.2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB0_3: // %if
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; CHECK-NEXT: cmp w2, w3
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; CHECK-NEXT: ccmp w0, w1, #0, ne
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; CHECK-NEXT: ccmp w4, w5, #0, ne
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; CHECK-NEXT: b.hs .LBB0_2
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; CHECK-NEXT: // %bb.1: // %if
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; CHECK-NEXT: mov w0, #1
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; CHECK-NEXT: str w0, [x6]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB0_2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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entry:
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%c0 = icmp eq i32 %s0, %s1
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%c1 = icmp ne i32 %s2, %s3
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@ -38,19 +36,17 @@ else:
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define i32 @and_ne_ult_ule(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
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; CHECK-LABEL: and_ne_ult_ule:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w0, w1
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; CHECK-NEXT: ccmp w2, w3, #2, ne
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; CHECK-NEXT: b.lo .LBB1_3
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; CHECK-NEXT: // %bb.1: // %entry
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; CHECK-NEXT: cmp w4, w5
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; CHECK-NEXT: b.ls .LBB1_3
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; CHECK-NEXT: // %bb.2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB1_3: // %if
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; CHECK-NEXT: cmp w2, w3
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; CHECK-NEXT: ccmp w0, w1, #4, lo
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; CHECK-NEXT: ccmp w4, w5, #0, eq
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; CHECK-NEXT: b.hi .LBB1_2
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; CHECK-NEXT: // %bb.1: // %if
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; CHECK-NEXT: mov w0, #1
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; CHECK-NEXT: str w0, [x6]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB1_2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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entry:
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%c0 = icmp ne i32 %s0, %s1
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%c1 = icmp ult i32 %s2, %s3
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@ -70,19 +66,17 @@ else:
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define i32 @and_ult_ule_ugt(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
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; CHECK-LABEL: and_ult_ule_ugt:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w0, w1
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; CHECK-NEXT: ccmp w2, w3, #2, lo
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; CHECK-NEXT: b.ls .LBB2_3
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; CHECK-NEXT: // %bb.1: // %entry
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; CHECK-NEXT: cmp w4, w5
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; CHECK-NEXT: b.hi .LBB2_3
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; CHECK-NEXT: // %bb.2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB2_3: // %if
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; CHECK-NEXT: cmp w2, w3
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; CHECK-NEXT: ccmp w0, w1, #2, ls
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; CHECK-NEXT: ccmp w4, w5, #2, hs
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; CHECK-NEXT: b.ls .LBB2_2
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; CHECK-NEXT: // %bb.1: // %if
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; CHECK-NEXT: mov w0, #1
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; CHECK-NEXT: str w0, [x6]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB2_2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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entry:
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%c0 = icmp ult i32 %s0, %s1
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%c1 = icmp ule i32 %s2, %s3
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@ -102,19 +96,17 @@ else:
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define i32 @and_ule_ugt_uge(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
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; CHECK-LABEL: and_ule_ugt_uge:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w0, w1
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; CHECK-NEXT: ccmp w2, w3, #0, ls
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; CHECK-NEXT: b.hi .LBB3_3
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; CHECK-NEXT: // %bb.1: // %entry
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; CHECK-NEXT: cmp w4, w5
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; CHECK-NEXT: b.hs .LBB3_3
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; CHECK-NEXT: // %bb.2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB3_3: // %if
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; CHECK-NEXT: cmp w2, w3
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; CHECK-NEXT: ccmp w0, w1, #2, hi
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; CHECK-NEXT: ccmp w4, w5, #2, hi
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; CHECK-NEXT: b.lo .LBB3_2
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; CHECK-NEXT: // %bb.1: // %if
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; CHECK-NEXT: mov w0, #1
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; CHECK-NEXT: str w0, [x6]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB3_2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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entry:
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%c0 = icmp ule i32 %s0, %s1
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%c1 = icmp ugt i32 %s2, %s3
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@ -134,19 +126,17 @@ else:
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define i32 @and_ugt_uge_slt(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
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; CHECK-LABEL: and_ugt_uge_slt:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w0, w1
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; CHECK-NEXT: ccmp w2, w3, #0, hi
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; CHECK-NEXT: b.hs .LBB4_3
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; CHECK-NEXT: // %bb.1: // %entry
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; CHECK-NEXT: cmp w4, w5
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; CHECK-NEXT: b.lt .LBB4_3
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; CHECK-NEXT: // %bb.2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB4_3: // %if
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; CHECK-NEXT: cmp w2, w3
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; CHECK-NEXT: ccmp w0, w1, #0, hs
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; CHECK-NEXT: ccmp w4, w5, #8, ls
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; CHECK-NEXT: b.ge .LBB4_2
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; CHECK-NEXT: // %bb.1: // %if
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; CHECK-NEXT: mov w0, #1
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; CHECK-NEXT: str w0, [x6]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB4_2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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entry:
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%c0 = icmp ugt i32 %s0, %s1
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%c1 = icmp uge i32 %s2, %s3
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@ -166,19 +156,17 @@ else:
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define i32 @and_uge_slt_sle(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
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; CHECK-LABEL: and_uge_slt_sle:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w0, w1
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; CHECK-NEXT: ccmp w2, w3, #0, hs
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; CHECK-NEXT: b.lt .LBB5_3
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; CHECK-NEXT: // %bb.1: // %entry
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; CHECK-NEXT: cmp w4, w5
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; CHECK-NEXT: b.le .LBB5_3
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; CHECK-NEXT: // %bb.2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB5_3: // %if
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; CHECK-NEXT: cmp w2, w3
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; CHECK-NEXT: ccmp w0, w1, #0, lt
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; CHECK-NEXT: ccmp w4, w5, #4, lo
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; CHECK-NEXT: b.gt .LBB5_2
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; CHECK-NEXT: // %bb.1: // %if
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; CHECK-NEXT: mov w0, #1
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; CHECK-NEXT: str w0, [x6]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB5_2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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entry:
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%c0 = icmp uge i32 %s0, %s1
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%c1 = icmp slt i32 %s2, %s3
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@ -198,19 +186,17 @@ else:
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define i32 @and_slt_sle_sgt(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
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; CHECK-LABEL: and_slt_sle_sgt:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w0, w1
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; CHECK-NEXT: ccmp w2, w3, #0, lt
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; CHECK-NEXT: b.le .LBB6_3
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; CHECK-NEXT: // %bb.1: // %entry
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; CHECK-NEXT: cmp w4, w5
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; CHECK-NEXT: b.gt .LBB6_3
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; CHECK-NEXT: // %bb.2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB6_3: // %if
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; CHECK-NEXT: cmp w2, w3
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; CHECK-NEXT: ccmp w0, w1, #0, le
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; CHECK-NEXT: ccmp w4, w5, #0, ge
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; CHECK-NEXT: b.le .LBB6_2
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; CHECK-NEXT: // %bb.1: // %if
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; CHECK-NEXT: mov w0, #1
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; CHECK-NEXT: str w0, [x6]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB6_2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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entry:
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%c0 = icmp slt i32 %s0, %s1
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%c1 = icmp sle i32 %s2, %s3
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@ -230,19 +216,17 @@ else:
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define i32 @and_sle_sgt_sge(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
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; CHECK-LABEL: and_sle_sgt_sge:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w0, w1
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; CHECK-NEXT: ccmp w2, w3, #4, le
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; CHECK-NEXT: b.gt .LBB7_3
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; CHECK-NEXT: // %bb.1: // %entry
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; CHECK-NEXT: cmp w4, w5
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; CHECK-NEXT: b.ge .LBB7_3
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; CHECK-NEXT: // %bb.2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB7_3: // %if
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; CHECK-NEXT: cmp w2, w3
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; CHECK-NEXT: ccmp w0, w1, #0, gt
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; CHECK-NEXT: ccmp w4, w5, #0, gt
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; CHECK-NEXT: b.lt .LBB7_2
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; CHECK-NEXT: // %bb.1: // %if
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; CHECK-NEXT: mov w0, #1
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; CHECK-NEXT: str w0, [x6]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB7_2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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entry:
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%c0 = icmp sle i32 %s0, %s1
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%c1 = icmp sgt i32 %s2, %s3
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