forked from OSchip/llvm-project
[mips][microMIPS] Implement BGEC, BGEUC, BLTC, BLTUC, BEQC and BNEC instructions
Differential Revision: http://reviews.llvm.org/D14206 llvm-svn: 266873
This commit is contained in:
Zoran Jovanovic
parent
f0bedf5343
commit
fdbd0a37c1
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@ -455,6 +455,16 @@ static DecodeStatus
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DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
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const void *Decoder);
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template <typename InsnType>
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static DecodeStatus
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DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
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const void *Decoder);
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template <typename InsnType>
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static DecodeStatus
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DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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@ -2133,3 +2143,87 @@ static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
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Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));
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return MCDisassembler::Success;
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}
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template <typename InsnType>
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static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn,
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uint64_t Address,
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const void *Decoder) {
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// We have:
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// 0b000111 ttttt sssss iiiiiiiiiiiiiiii
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// Invalid if rt == 0
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// BGTZALC_MMR6 if rs == 0 && rt != 0
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// BLTZALC_MMR6 if rs != 0 && rs == rt
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// BLTUC_MMR6 if rs != 0 && rs != rt
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InsnType Rt = fieldFromInstruction(insn, 21, 5);
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InsnType Rs = fieldFromInstruction(insn, 16, 5);
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InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2;
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bool HasRs = false;
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bool HasRt = false;
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if (Rt == 0)
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return MCDisassembler::Fail;
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else if (Rs == 0) {
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MI.setOpcode(Mips::BGTZALC_MMR6);
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HasRt = true;
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}
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else if (Rs == Rt) {
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MI.setOpcode(Mips::BLTZALC_MMR6);
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HasRs = true;
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}
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else {
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MI.setOpcode(Mips::BLTUC_MMR6);
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HasRs = true;
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HasRt = true;
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}
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if (HasRs)
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MI.addOperand(
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MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
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if (HasRt)
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MI.addOperand(
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MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
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MI.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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template <typename InsnType>
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static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn,
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uint64_t Address,
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const void *Decoder) {
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// We have:
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// 0b000110 ttttt sssss iiiiiiiiiiiiiiii
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// Invalid if rs == 0
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// BLEZALC_MMR6 if rs == 0 && rt != 0
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// BGEZALC_MMR6 if rs == rt && rt != 0
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// BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0
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InsnType Rt = fieldFromInstruction(insn, 21, 5);
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InsnType Rs = fieldFromInstruction(insn, 16, 5);
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InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2;
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bool HasRs = false;
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if (Rt == 0)
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return MCDisassembler::Fail;
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else if (Rs == 0)
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MI.setOpcode(Mips::BLEZALC_MMR6);
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else if (Rs == Rt)
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MI.setOpcode(Mips::BGEZALC_MMR6);
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else {
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HasRs = true;
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MI.setOpcode(Mips::BGEUC_MMR6);
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}
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if (HasRs)
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MI.addOperand(
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MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
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MI.addOperand(
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MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
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MI.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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@ -14,6 +14,7 @@
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class MMR6Arch<string opstr> {
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string Arch = "micromipsr6";
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string BaseOpcode = opstr;
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string DecoderNamespace = "MicroMipsR6";
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}
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// Class used for microMIPS32r6 and microMIPS64r6 instructions.
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@ -22,6 +23,24 @@ class MicroMipsR6Inst16 : PredicateControl {
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let InsnPredicates = [HasMicroMips32r6];
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}
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//===----------------------------------------------------------------------===//
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//
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// Disambiguators
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//
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//===----------------------------------------------------------------------===//
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//
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// Some encodings are ambiguous except by comparing field values.
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class MMDecodeDisambiguatedBy<string Name> : DecodeDisambiguates<Name> {
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string DecoderNamespace = "MicroMipsR6_Ambiguous";
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}
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//===----------------------------------------------------------------------===//
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//
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// Encoding Formats
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//
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//===----------------------------------------------------------------------===//
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class BC16_FM_MM16R6 {
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bits<10> offset;
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@ -449,7 +468,8 @@ class LOAD_UPPER_IMM_FM_MMR6 {
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let Inst{15-0} = imm16;
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}
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class CMP_BRANCH_1R_RT_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
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class CMP_BRANCH_1R_RT_OFF16_FM_MMR6<string instr_asm, bits<6> funct>
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: MMR6Arch<instr_asm>, MipsR6Inst {
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bits<5> rt;
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bits<16> offset;
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@ -461,7 +481,8 @@ class CMP_BRANCH_1R_RT_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
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let Inst{15-0} = offset;
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}
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class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
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class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<string instr_asm, bits<6> funct>
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: MMR6Arch<instr_asm>, MipsR6Inst {
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bits<5> rt;
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bits<16> offset;
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@ -948,3 +969,18 @@ class POOL32B_LDWC2_SDWC2_FM_MMR6<string instr_asm, bits<4> funct>
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let Inst{11} = 0;
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let Inst{10-0} = offset;
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}
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class CMP_BRANCH_2R_OFF16_FM_MMR6<string opstr, bits<6> funct>
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: MipsR6Inst, MMR6Arch<opstr> {
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bits<5> rt;
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bits<5> rs;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = funct;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-0} = offset;
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}
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@ -40,12 +40,24 @@ class BEQZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x23>;
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class BNEZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x2b>;
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class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
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class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;
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class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011101>;
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class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011111>;
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class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b111000>;
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class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b111000>;
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class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b110000>;
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class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b110000>;
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class BGEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgec", 0b111001>;
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class BGEUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgeuc", 0b110000>,
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DecodeDisambiguates<"BlezGroupBranchMMR6">;
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class BLTC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bltc", 0b110001>;
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class BLTUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bltuc", 0b111000>,
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DecodeDisambiguates<"BgtzGroupBranchMMR6">;
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class BEQC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"beqc", 0b011101>;
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class BNEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bnec", 0b011111>;
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class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"beqzalc", 0b011101>;
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class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bnezalc", 0b011111>;
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class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bgtzalc", 0b111000>,
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MMDecodeDisambiguatedBy<"BgtzGroupBranchMMR6">;
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class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bltzalc", 0b111000>,
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MMDecodeDisambiguatedBy<"BgtzGroupBranchMMR6">;
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class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bgezalc", 0b110000>,
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MMDecodeDisambiguatedBy<"BlezGroupBranchMMR6">;
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class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"blezalc", 0b110000>,
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MMDecodeDisambiguatedBy<"BlezGroupBranchMMR6">;
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class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
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class CFC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"cfc1", 0b01000000>;
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class CFC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"cfc2", 0b1100110100>;
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@ -191,7 +203,7 @@ class TLBINVF_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinvf", 0x14d>;
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class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
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RegisterOperand GPROpnd>
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: BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
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: BRANCH_DESC_BASE {
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dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
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dag OutOperandList = (outs);
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string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
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@ -228,6 +240,27 @@ class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
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list<Register> Defs = [RA];
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}
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class CMP_CBR_2R_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
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RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
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dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
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dag OutOperandList = (outs);
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string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
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list<Register> Defs = [AT];
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}
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class BGEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgec", brtarget_mm,
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GPR32Opnd>;
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class BGEUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgeuc", brtarget_mm,
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GPR32Opnd>;
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class BLTC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltc", brtarget_mm,
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GPR32Opnd>;
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class BLTUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltuc", brtarget_mm,
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GPR32Opnd>;
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class BEQC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"beqc", brtarget_mm,
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GPR32Opnd>;
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class BNEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bnec", brtarget_mm,
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GPR32Opnd>;
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/// Floating Point Instructions
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class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>;
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class FADD_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.d", 1, 0b00110000>;
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@ -1140,14 +1173,6 @@ def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def BEQZALC_MMR6 : R6MMR6Rel, BEQZALC_MMR6_ENC, BEQZALC_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
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@ -1426,6 +1451,21 @@ def TLBINVF_MMR6 : StdMMR6Rel, TLBINVF_MMR6_ENC, TLBINVF_MMR6_DESC,
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ISA_MICROMIPS32R6;
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}
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def BGEC_MMR6 : R6MMR6Rel, BGEC_MMR6_ENC, BGEC_MMR6_DESC, ISA_MICROMIPS32R6;
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def BGEUC_MMR6 : R6MMR6Rel, BGEUC_MMR6_ENC, BGEUC_MMR6_DESC, ISA_MICROMIPS32R6;
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def BLTC_MMR6 : R6MMR6Rel, BLTC_MMR6_ENC, BLTC_MMR6_DESC, ISA_MICROMIPS32R6;
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def BLTUC_MMR6 : R6MMR6Rel, BLTUC_MMR6_ENC, BLTUC_MMR6_DESC, ISA_MICROMIPS32R6;
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def BEQC_MMR6 : R6MMR6Rel, BEQC_MMR6_ENC, BEQC_MMR6_DESC, ISA_MICROMIPS32R6;
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def BNEC_MMR6 : R6MMR6Rel, BNEC_MMR6_ENC, BNEC_MMR6_DESC, ISA_MICROMIPS32R6;
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def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
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ISA_MICROMIPS32R6;
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//===----------------------------------------------------------------------===//
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//
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// MicroMips instruction aliases
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@ -315,7 +315,8 @@ class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE,
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}
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class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
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RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
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RegisterOperand GPROpnd> : BRANCH_DESC_BASE,
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MipsR6Arch<instr_asm> {
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dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
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dag OutOperandList = (outs);
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string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
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@ -718,11 +719,11 @@ def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6, HARDFLOAT;
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def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6;
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def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6;
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def BC : R6MMR6Rel, BC_ENC, BC_DESC, ISA_MIPS32R6;
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def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
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def BEQC : R6MMR6Rel, BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
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def BEQZALC : R6MMR6Rel, BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;
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def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
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def BGEC : BGEC_ENC, BGEC_DESC, ISA_MIPS32R6;
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def BGEUC : BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6;
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def BGEC : R6MMR6Rel, BGEC_ENC, BGEC_DESC, ISA_MIPS32R6;
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def BGEUC : R6MMR6Rel, BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6;
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def BGEZALC : R6MMR6Rel, BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;
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def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
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def BGTZALC : R6MMR6Rel, BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6;
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@ -730,11 +731,11 @@ def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
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def BITSWAP : R6MMR6Rel, BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
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def BLEZALC : R6MMR6Rel, BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6;
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def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
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def BLTC : BLTC_ENC, BLTC_DESC, ISA_MIPS32R6;
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def BLTUC : BLTUC_ENC, BLTUC_DESC, ISA_MIPS32R6;
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def BLTC : R6MMR6Rel, BLTC_ENC, BLTC_DESC, ISA_MIPS32R6;
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def BLTUC : R6MMR6Rel, BLTUC_ENC, BLTUC_DESC, ISA_MIPS32R6;
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def BLTZALC : R6MMR6Rel, BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;
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def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
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def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
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def BNEC : R6MMR6Rel, BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
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def BNEZALC : R6MMR6Rel, BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
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def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
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def BNVC : BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;
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||||
|
|
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|
@ -38,6 +38,12 @@
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0x00 0xa4 0x1a 0x50 # CHECK: and $3, $4, $5
|
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0xd0 0x64 0x04 0xd2 # CHECK: andi $3, $4, 1234
|
||||
0x10 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23
|
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0x74 0x83 0x00 0x08 # CHECK: beqc $3, $4, 16
|
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0xe4 0x83 0x00 0x08 # CHECK: bgec $3, $4, 16
|
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0xc0 0x83 0x00 0x08 # CHECK: bgeuc $3, $4, 16
|
||||
0xc4 0x83 0x00 0x08 # CHECK: bltc $3, $4, 16
|
||||
0xe0 0x83 0x00 0x08 # CHECK: bltuc $3, $4, 16
|
||||
0x7c 0x83 0x00 0x08 # CHECK: bnec $3, $4, 16
|
||||
0x74 0x40 0x02 0x9a # CHECK: beqzalc $2, 1332
|
||||
0x7c 0x40 0x02 0x9a # CHECK: bnezalc $2, 1332
|
||||
0xc0 0x42 0x02 0x9a # CHECK: bgezalc $2, 1332
|
||||
|
|
|
|||
|
|
@ -20,6 +20,12 @@
|
|||
auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0x78,0x7e,0xff,0xff]
|
||||
align $4, $2, $3, 2 # CHECK: align $4, $2, $3, 2 # encoding: [0x00,0x43,0x24,0x1f]
|
||||
aui $3,$2,-23 # CHECK: aui $3, $2, -23 # encoding: [0x10,0x62,0xff,0xe9]
|
||||
beqc $3,$4, 16 # CHECK: beqc $3, $4, 16 # encoding: [0x74,0x83,0x00,0x08]
|
||||
bgec $3,$4, 16 # CHECK: bgec $3, $4, 16 # encoding: [0xe4,0x83,0x00,0x08]
|
||||
bgeuc $3,$4, 16 # CHECK: bgeuc $3, $4, 16 # encoding: [0xc0,0x83,0x00,0x08]
|
||||
bltc $3,$4, 16 # CHECK: bltc $3, $4, 16 # encoding: [0xc4,0x83,0x00,0x08]
|
||||
bltuc $3,$4, 16 # CHECK: bltuc $3, $4, 16 # encoding: [0xe0,0x83,0x00,0x08]
|
||||
bnec $3,$4, 16 # CHECK: bnec $3, $4, 16 # encoding: [0x7c,0x83,0x00,0x08]
|
||||
beqzalc $2, 1332 # CHECK: beqzalc $2, 1332 # encoding: [0x74,0x40,0x02,0x9a]
|
||||
bnezalc $2, 1332 # CHECK: bnezalc $2, 1332 # encoding: [0x7c,0x40,0x02,0x9a]
|
||||
bgezalc $2, 1332 # CHECK: bgezalc $2, 1332 # encoding: [0xc0,0x42,0x02,0x9a]
|
||||
|
|
|
|||
Loading…
Reference in New Issue