forked from OSchip/llvm-project
[Hexagon] Replacing intrinsics for halfword adds and max/min word/dword.
llvm-svn: 227322
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@ -279,14 +279,6 @@ void sys::DontRemoveFileOnSignal(StringRef Filename) {
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/// PrintStackTraceOnErrorSignal - When an error signal (such as SIBABRT or
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/// SIGSEGV) is delivered to the process, print a stack trace and then exit.
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void sys::PrintStackTraceOnErrorSignal() {
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// Don't pop up any dialog boxes.
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// We're already handling writing a "something went wrong" message.
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_set_abort_behavior(0, _WRITE_ABORT_MSG);
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// Disable Dr. Watson.
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_set_abort_behavior(0, _CALL_REPORTFAULT);
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// Disable standard error dialog box.
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SetErrorMode(SEM_FAILCRITICALERRORS | SEM_NOGPFAULTERRORBOX);
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RegisterHandler();
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LeaveCriticalSection(&CriticalSection);
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}
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@ -255,6 +255,61 @@ def : T_PRR_pat <M2_mpyud_nac_hl_s1, int_hexagon_M2_mpyud_nac_hl_s1>;
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def : T_PRR_pat <M2_mpyud_nac_lh_s1, int_hexagon_M2_mpyud_nac_lh_s1>;
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def : T_PRR_pat <M2_mpyud_nac_ll_s1, int_hexagon_M2_mpyud_nac_ll_s1>;
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//===----------------------------------------------------------------------===//
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// Add/Subtract halfword
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// Rd=add(Rt.L,Rs.[HL])[:sat]
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// Rd=sub(Rt.L,Rs.[HL])[:sat]
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// Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16]
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// Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16]
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//===----------------------------------------------------------------------===//
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//Rd=add(Rt.L,Rs.[LH])
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def : T_RR_pat <A2_addh_l16_ll, int_hexagon_A2_addh_l16_ll>;
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def : T_RR_pat <A2_addh_l16_hl, int_hexagon_A2_addh_l16_hl>;
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//Rd=add(Rt.L,Rs.[LH]):sat
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def : T_RR_pat <A2_addh_l16_sat_ll, int_hexagon_A2_addh_l16_sat_ll>;
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def : T_RR_pat <A2_addh_l16_sat_hl, int_hexagon_A2_addh_l16_sat_hl>;
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//Rd=sub(Rt.L,Rs.[LH])
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def : T_RR_pat <A2_subh_l16_ll, int_hexagon_A2_subh_l16_ll>;
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def : T_RR_pat <A2_subh_l16_hl, int_hexagon_A2_subh_l16_hl>;
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//Rd=sub(Rt.L,Rs.[LH]):sat
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def : T_RR_pat <A2_subh_l16_sat_ll, int_hexagon_A2_subh_l16_sat_ll>;
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def : T_RR_pat <A2_subh_l16_sat_hl, int_hexagon_A2_subh_l16_sat_hl>;
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//Rd=add(Rt.[LH],Rs.[LH]):<<16
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def : T_RR_pat <A2_addh_h16_ll, int_hexagon_A2_addh_h16_ll>;
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def : T_RR_pat <A2_addh_h16_lh, int_hexagon_A2_addh_h16_lh>;
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def : T_RR_pat <A2_addh_h16_hl, int_hexagon_A2_addh_h16_hl>;
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def : T_RR_pat <A2_addh_h16_hh, int_hexagon_A2_addh_h16_hh>;
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//Rd=sub(Rt.[LH],Rs.[LH]):<<16
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def : T_RR_pat <A2_subh_h16_ll, int_hexagon_A2_subh_h16_ll>;
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def : T_RR_pat <A2_subh_h16_lh, int_hexagon_A2_subh_h16_lh>;
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def : T_RR_pat <A2_subh_h16_hl, int_hexagon_A2_subh_h16_hl>;
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def : T_RR_pat <A2_subh_h16_hh, int_hexagon_A2_subh_h16_hh>;
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//Rd=add(Rt.[LH],Rs.[LH]):sat:<<16
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def : T_RR_pat <A2_addh_h16_sat_ll, int_hexagon_A2_addh_h16_sat_ll>;
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def : T_RR_pat <A2_addh_h16_sat_lh, int_hexagon_A2_addh_h16_sat_lh>;
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def : T_RR_pat <A2_addh_h16_sat_hl, int_hexagon_A2_addh_h16_sat_hl>;
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def : T_RR_pat <A2_addh_h16_sat_hh, int_hexagon_A2_addh_h16_sat_hh>;
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//Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16
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def : T_RR_pat <A2_subh_h16_sat_ll, int_hexagon_A2_subh_h16_sat_ll>;
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def : T_RR_pat <A2_subh_h16_sat_lh, int_hexagon_A2_subh_h16_sat_lh>;
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def : T_RR_pat <A2_subh_h16_sat_hl, int_hexagon_A2_subh_h16_sat_hl>;
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def : T_RR_pat <A2_subh_h16_sat_hh, int_hexagon_A2_subh_h16_sat_hh>;
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// ALU64 / ALU / min max
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def : T_RR_pat<A2_max, int_hexagon_A2_max>;
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def : T_RR_pat<A2_min, int_hexagon_A2_min>;
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def : T_RR_pat<A2_maxu, int_hexagon_A2_maxu>;
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def : T_RR_pat<A2_minu, int_hexagon_A2_minu>;
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/********************************************************************
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* ALU32/ALU *
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*********************************************************************/
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@ -2300,37 +2355,6 @@ def HEXAGON_A2_addp:
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def HEXAGON_A2_addsat:
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si_ALU64_sisi_sat <"add", int_hexagon_A2_addsat>;
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// ALU64 / ALU / Add halfword.
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// Even though the definition says hl, it should be lh -
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//so DON'T change the class " si_ALU64_sisi_l16_lh " it inherits.
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def HEXAGON_A2_addh_l16_hl:
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si_ALU64_sisi_l16_lh <"add", int_hexagon_A2_addh_l16_hl>;
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def HEXAGON_A2_addh_l16_ll:
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si_ALU64_sisi_l16_ll <"add", int_hexagon_A2_addh_l16_ll>;
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def HEXAGON_A2_addh_l16_sat_hl:
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si_ALU64_sisi_l16_sat_lh <"add", int_hexagon_A2_addh_l16_sat_hl>;
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def HEXAGON_A2_addh_l16_sat_ll:
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si_ALU64_sisi_l16_sat_ll <"add", int_hexagon_A2_addh_l16_sat_ll>;
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def HEXAGON_A2_addh_h16_hh:
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si_ALU64_sisi_h16_hh <"add", int_hexagon_A2_addh_h16_hh>;
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def HEXAGON_A2_addh_h16_hl:
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si_ALU64_sisi_h16_hl <"add", int_hexagon_A2_addh_h16_hl>;
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def HEXAGON_A2_addh_h16_lh:
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si_ALU64_sisi_h16_lh <"add", int_hexagon_A2_addh_h16_lh>;
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def HEXAGON_A2_addh_h16_ll:
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si_ALU64_sisi_h16_ll <"add", int_hexagon_A2_addh_h16_ll>;
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def HEXAGON_A2_addh_h16_sat_hh:
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si_ALU64_sisi_h16_sat_hh <"add", int_hexagon_A2_addh_h16_sat_hh>;
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def HEXAGON_A2_addh_h16_sat_hl:
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si_ALU64_sisi_h16_sat_hl <"add", int_hexagon_A2_addh_h16_sat_hl>;
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def HEXAGON_A2_addh_h16_sat_lh:
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si_ALU64_sisi_h16_sat_lh <"add", int_hexagon_A2_addh_h16_sat_lh>;
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def HEXAGON_A2_addh_h16_sat_ll:
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si_ALU64_sisi_h16_sat_ll <"add", int_hexagon_A2_addh_h16_sat_ll>;
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// ALU64 / ALU / Compare.
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def HEXAGON_C2_cmpeqp:
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qi_ALU64_didi <"cmp.eq", int_hexagon_C2_cmpeqp>;
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@ -2347,55 +2371,12 @@ def HEXAGON_A2_orp:
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def HEXAGON_A2_xorp:
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di_ALU64_didi <"xor", int_hexagon_A2_xorp>;
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// ALU64 / ALU / Maximum.
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def HEXAGON_A2_max:
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si_ALU64_sisi <"max", int_hexagon_A2_max>;
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def HEXAGON_A2_maxu:
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si_ALU64_sisi <"maxu", int_hexagon_A2_maxu>;
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// ALU64 / ALU / Minimum.
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def HEXAGON_A2_min:
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si_ALU64_sisi <"min", int_hexagon_A2_min>;
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def HEXAGON_A2_minu:
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si_ALU64_sisi <"minu", int_hexagon_A2_minu>;
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// ALU64 / ALU / Subtract.
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def HEXAGON_A2_subp:
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di_ALU64_didi <"sub", int_hexagon_A2_subp>;
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def HEXAGON_A2_subsat:
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si_ALU64_sisi_sat <"sub", int_hexagon_A2_subsat>;
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// ALU64 / ALU / Subtract halfword.
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// Even though the definition says hl, it should be lh -
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//so DON'T change the class " si_ALU64_sisi_l16_lh " it inherits.
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def HEXAGON_A2_subh_l16_hl:
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si_ALU64_sisi_l16_lh <"sub", int_hexagon_A2_subh_l16_hl>;
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def HEXAGON_A2_subh_l16_ll:
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si_ALU64_sisi_l16_ll <"sub", int_hexagon_A2_subh_l16_ll>;
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def HEXAGON_A2_subh_l16_sat_hl:
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si_ALU64_sisi_l16_sat_lh <"sub", int_hexagon_A2_subh_l16_sat_hl>;
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def HEXAGON_A2_subh_l16_sat_ll:
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si_ALU64_sisi_l16_sat_ll <"sub", int_hexagon_A2_subh_l16_sat_ll>;
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def HEXAGON_A2_subh_h16_hh:
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si_ALU64_sisi_h16_hh <"sub", int_hexagon_A2_subh_h16_hh>;
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def HEXAGON_A2_subh_h16_hl:
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si_ALU64_sisi_h16_hl <"sub", int_hexagon_A2_subh_h16_hl>;
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def HEXAGON_A2_subh_h16_lh:
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si_ALU64_sisi_h16_lh <"sub", int_hexagon_A2_subh_h16_lh>;
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def HEXAGON_A2_subh_h16_ll:
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si_ALU64_sisi_h16_ll <"sub", int_hexagon_A2_subh_h16_ll>;
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def HEXAGON_A2_subh_h16_sat_hh:
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si_ALU64_sisi_h16_sat_hh <"sub", int_hexagon_A2_subh_h16_sat_hh>;
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def HEXAGON_A2_subh_h16_sat_hl:
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si_ALU64_sisi_h16_sat_hl <"sub", int_hexagon_A2_subh_h16_sat_hl>;
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def HEXAGON_A2_subh_h16_sat_lh:
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si_ALU64_sisi_h16_sat_lh <"sub", int_hexagon_A2_subh_h16_sat_lh>;
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def HEXAGON_A2_subh_h16_sat_ll:
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si_ALU64_sisi_h16_sat_ll <"sub", int_hexagon_A2_subh_h16_sat_ll>;
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// ALU64 / ALU / Transfer register.
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def HEXAGON_A2_tfrp:
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di_ALU64_di <"", int_hexagon_A2_tfrp>;
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