forked from OSchip/llvm-project
Tail duplication can mix incompatible registers in phi nodes
Do not tail duplicate blocks where the successor has a phi node, and the corresponding value in that phi node uses a subregister. http://reviews.llvm.org/D13922 llvm-svn: 250877
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@ -607,6 +607,27 @@ TailDuplicatePass::shouldTailDuplicate(const MachineFunction &MF,
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return false;
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}
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// Check if any of the successors of TailBB has a PHI node in which the
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// value corresponding to TailBB uses a subregister.
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// If a phi node uses a register paired with a subregister, the actual
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// "value type" of the phi may differ from the type of the register without
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// any subregisters. Due to a bug, tail duplication may add a new operand
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// without a necessary subregister, producing an invalid code. This is
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// demonstrated by test/CodeGen/Hexagon/tail-dup-subreg-abort.ll.
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// Disable tail duplication for this case for now, until the problem is
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// fixed.
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for (auto SB : TailBB.successors()) {
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for (auto &I : *SB) {
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if (!I.isPHI())
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break;
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unsigned Idx = getPHISrcRegOpIdx(&I, &TailBB);
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assert(Idx != 0);
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MachineOperand &PU = I.getOperand(Idx);
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if (PU.getSubReg() != 0)
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return false;
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}
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}
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if (HasIndirectbr && PreRegAlloc)
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return true;
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@ -0,0 +1,28 @@
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; RUN: llc -march=hexagon -O2 -disable-cgp < %s
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; REQUIRES: asserts
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;
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; Tail duplication can ignore subregister information on PHI nodes, and as
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; a result, generate COPY instructions between registers of different classes.
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; This could lead to HexagonInstrInfo::copyPhysReg aborting on an unhandled
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; src/dst combination.
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;
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define i32 @foo(i32 %x, i64 %y) nounwind {
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entry:
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%a = icmp slt i32 %x, 0
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%lo = trunc i64 %y to i32
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br i1 %a, label %next, label %tail
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tail:
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br label %join
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next:
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%c = icmp eq i32 %x, 0
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br i1 %c, label %b1, label %tail
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b1:
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%t1 = lshr i64 %y, 32
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%hi = trunc i64 %t1 to i32
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br label %join
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join:
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%val = phi i32 [ %hi, %b1 ], [ %lo, %tail ]
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ret i32 %val
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}
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