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llvm-svn: 21457
This commit is contained in:
Misha Brukman 2005-04-22 18:06:01 +00:00
parent 36c6bc1bf4
commit fd8c2265fa
3 changed files with 45 additions and 33 deletions
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38
llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp
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@ -876,10 +876,12 @@ void V8ISel::visitCallInst(CallInst &I) {
if (getClassB (I.getOperand (i)->getType ()) < cLong) {
// Schlep it over into the incoming arg register
if (ArgOffset < 92) {
assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
assert (OAR != OAREnd &&
"About to dereference past end of OutgoingArgRegs");
BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
} else {
BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (ArgReg);
BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset)
.addReg (ArgReg);
}
ArgOffset += 4;
} else if (getClassB (I.getOperand (i)->getType ()) == cFloat) {
@ -888,11 +890,13 @@ void V8ISel::visitCallInst(CallInst &I) {
// memory to get them out of FP registers. (Bleh!)
unsigned FltAlign = TM.getTargetData().getFloatAlignment();
int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
BuildMI (BB, V8::STFri, 3).addFrameIndex (FI).addSImm (0).addReg (ArgReg);
assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
BuildMI (BB, V8::STFri, 3).addFrameIndex(FI).addSImm(0).addReg(ArgReg);
assert (OAR != OAREnd &&
"About to dereference past end of OutgoingArgRegs");
BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (0);
} else {
BuildMI (BB, V8::STFri, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (ArgReg);
BuildMI (BB, V8::STFri, 3).addReg (V8::SP).addSImm (ArgOffset)
.addReg (ArgReg);
}
ArgOffset += 4;
} else if (getClassB (I.getOperand (i)->getType ()) == cDouble) {
@ -904,38 +908,46 @@ void V8ISel::visitCallInst(CallInst &I) {
int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
BuildMI (BB, V8::STDFri, 3).addFrameIndex (FI).addSImm (0).addReg (ArgReg);
if (ArgOffset < 92 && OAR != OAREnd) {
assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
assert (OAR != OAREnd &&
"About to dereference past end of OutgoingArgRegs");
BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (0);
} else {
unsigned TempReg = makeAnotherReg (Type::IntTy);
BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (0);
BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (TempReg);
BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset)
.addReg (TempReg);
}
ArgOffset += 4;
if (ArgOffset < 92 && OAR != OAREnd) {
assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
assert (OAR != OAREnd &&
"About to dereference past end of OutgoingArgRegs");
BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (4);
} else {
unsigned TempReg = makeAnotherReg (Type::IntTy);
BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (4);
BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (TempReg);
BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset)
.addReg (TempReg);
}
ArgOffset += 4;
} else if (getClassB (I.getOperand (i)->getType ()) == cLong) {
// do the first half...
if (ArgOffset < 92) {
assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
assert (OAR != OAREnd &&
"About to dereference past end of OutgoingArgRegs");
BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
} else {
BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (ArgReg);
BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset)
.addReg (ArgReg);
}
ArgOffset += 4;
// ...then do the second half
if (ArgOffset < 92) {
assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
assert (OAR != OAREnd &&
"About to dereference past end of OutgoingArgRegs");
BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg+1);
} else {
BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (ArgReg+1);
BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset)
.addReg (ArgReg+1);
}
ArgOffset += 4;
} else {