forked from OSchip/llvm-project
[mips][micromips] Add predicate 'InMicroMips' at CodeGen patterns for microMIPS instructions
Differential Revision: http://reviews.llvm.org/D6198 llvm-svn: 221780
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@ -510,6 +510,8 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
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}
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let Predicates = [InMicroMips] in {
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//===----------------------------------------------------------------------===//
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// MicroMips arbitrary patterns that map to one or more instructions
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//===----------------------------------------------------------------------===//
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@ -533,6 +535,5 @@ def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
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// MicroMips instruction aliases
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//===----------------------------------------------------------------------===//
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let Predicates = [InMicroMips] in {
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def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;
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}
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@ -0,0 +1,24 @@
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; RUN: llc -march=mipsel -mcpu=mips32r2 -O1 -fast-isel=true -mips-fast-isel -filetype=obj %s -o - \
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; RUN: | llvm-objdump -arch mipsel -mcpu=mips32r2 -d - | FileCheck %s
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; This test checks that encoding for srl is correct when fast-isel for mips32r2 is used.
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%struct.s = type { [4 x i8], i32 }
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define i32 @main() nounwind uwtable {
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entry:
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%foo = alloca %struct.s, align 4
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%0 = bitcast %struct.s* %foo to i32*
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%bf.load = load i32* %0, align 4
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%bf.lshr = lshr i32 %bf.load, 2
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%cmp = icmp ne i32 %bf.lshr, 2
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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unreachable
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if.end:
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ret i32 0
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}
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; CHECK: srl ${{[0-9]+}}, ${{[0-9]+}}, {{[0-9]+}}
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