forked from OSchip/llvm-project
[X86][AArch64][NFC] Add tests for vector masked merge unfolding
Summary: This is [[ https://bugs.llvm.org/show_bug.cgi?id=37104 | PR37104 ]]. [[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]] will introduce an IR canonicalization that is likely bad for the end assembly. Previously, `andps`+`andnps` / `bsl` would be generated. (see `@out`) Now, they would no longer be generated (see `@in`). Differential Revision: https://reviews.llvm.org/D46008 llvm-svn: 332903
This commit is contained in:
Roman Lebedev
parent
df8f754792
commit
fd79bc3aa2
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@ -0,0 +1,232 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
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; ============================================================================ ;
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; Various cases with %x and/or %y being a constant
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; ============================================================================ ;
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define <4 x i32> @out_constant_varx_mone(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) {
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; CHECK-LABEL: out_constant_varx_mone:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and v0.16b, v2.16b, v0.16b
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; CHECK-NEXT: orn v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: ret
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%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
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%mx = and <4 x i32> %mask, %x
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%my = and <4 x i32> %notmask, <i32 -1, i32 -1, i32 -1, i32 -1>
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%r = or <4 x i32> %mx, %my
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ret <4 x i32> %r
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}
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define <4 x i32> @in_constant_varx_mone(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) {
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; CHECK-LABEL: in_constant_varx_mone:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bic v0.16b, v2.16b, v0.16b
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; CHECK-NEXT: mvn v0.16b, v0.16b
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; CHECK-NEXT: ret
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%n0 = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> ; %x
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%n1 = and <4 x i32> %n0, %mask
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%r = xor <4 x i32> %n1, <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %r
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}
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; This is not a canonical form. Testing for completeness only.
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define <4 x i32> @out_constant_varx_mone_invmask(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) {
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; CHECK-LABEL: out_constant_varx_mone_invmask:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bic v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: ret
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%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
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%mx = and <4 x i32> %notmask, %x
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%my = and <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
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%r = or <4 x i32> %mx, %my
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ret <4 x i32> %r
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}
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; This is not a canonical form. Testing for completeness only.
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define <4 x i32> @in_constant_varx_mone_invmask(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) {
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; CHECK-LABEL: in_constant_varx_mone_invmask:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn v0.16b, v0.16b
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; CHECK-NEXT: bic v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: mvn v0.16b, v0.16b
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; CHECK-NEXT: ret
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%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
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%n0 = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> ; %x
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%n1 = and <4 x i32> %n0, %notmask
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%r = xor <4 x i32> %n1, <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %r
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}
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define <4 x i32> @out_constant_varx_42(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) {
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; CHECK-LABEL: out_constant_varx_42:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.4s, #42
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; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: ret
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%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
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%mx = and <4 x i32> %mask, %x
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%my = and <4 x i32> %notmask, <i32 42, i32 42, i32 42, i32 42>
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%r = or <4 x i32> %mx, %my
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ret <4 x i32> %r
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}
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define <4 x i32> @in_constant_varx_42(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) {
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; CHECK-LABEL: in_constant_varx_42:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.4s, #42
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; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%n0 = xor <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42> ; %x
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%n1 = and <4 x i32> %n0, %mask
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%r = xor <4 x i32> %n1, <i32 42, i32 42, i32 42, i32 42>
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ret <4 x i32> %r
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}
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; This is not a canonical form. Testing for completeness only.
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define <4 x i32> @out_constant_varx_42_invmask(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) {
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; CHECK-LABEL: out_constant_varx_42_invmask:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.4s, #42
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; CHECK-NEXT: bsl v2.16b, v1.16b, v0.16b
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: ret
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%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
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%mx = and <4 x i32> %notmask, %x
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%my = and <4 x i32> %mask, <i32 42, i32 42, i32 42, i32 42>
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%r = or <4 x i32> %mx, %my
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ret <4 x i32> %r
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}
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; This is not a canonical form. Testing for completeness only.
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define <4 x i32> @in_constant_varx_42_invmask(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) {
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; CHECK-LABEL: in_constant_varx_42_invmask:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.4s, #42
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; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: bic v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
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%n0 = xor <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42> ; %x
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%n1 = and <4 x i32> %n0, %notmask
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%r = xor <4 x i32> %n1, <i32 42, i32 42, i32 42, i32 42>
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ret <4 x i32> %r
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}
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define <4 x i32> @out_constant_mone_vary(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) {
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; CHECK-LABEL: out_constant_mone_vary:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bic v0.16b, v1.16b, v2.16b
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; CHECK-NEXT: orr v0.16b, v2.16b, v0.16b
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; CHECK-NEXT: ret
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%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
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%mx = and <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
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%my = and <4 x i32> %notmask, %y
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%r = or <4 x i32> %mx, %my
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ret <4 x i32> %r
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}
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define <4 x i32> @in_constant_mone_vary(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) {
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; CHECK-LABEL: in_constant_mone_vary:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bic v0.16b, v2.16b, v1.16b
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; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%n0 = xor <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %y ; %x
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%n1 = and <4 x i32> %n0, %mask
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%r = xor <4 x i32> %n1, %y
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ret <4 x i32> %r
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}
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; This is not a canonical form. Testing for completeness only.
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define <4 x i32> @out_constant_mone_vary_invmask(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) {
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; CHECK-LABEL: out_constant_mone_vary_invmask:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and v0.16b, v2.16b, v1.16b
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; CHECK-NEXT: orn v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: ret
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%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
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%mx = and <4 x i32> %notmask, <i32 -1, i32 -1, i32 -1, i32 -1>
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%my = and <4 x i32> %mask, %y
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%r = or <4 x i32> %mx, %my
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ret <4 x i32> %r
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}
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; This is not a canonical form. Testing for completeness only.
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define <4 x i32> @in_constant_mone_vary_invmask(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) {
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; CHECK-LABEL: in_constant_mone_vary_invmask:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn v0.16b, v1.16b
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; CHECK-NEXT: bic v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
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%n0 = xor <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %y ; %x
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%n1 = and <4 x i32> %n0, %notmask
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%r = xor <4 x i32> %n1, %y
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ret <4 x i32> %r
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}
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define <4 x i32> @out_constant_42_vary(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) {
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; CHECK-LABEL: out_constant_42_vary:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: movi v2.4s, #42
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; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b
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; CHECK-NEXT: ret
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%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
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%mx = and <4 x i32> %mask, <i32 42, i32 42, i32 42, i32 42>
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%my = and <4 x i32> %notmask, %y
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%r = or <4 x i32> %mx, %my
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ret <4 x i32> %r
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}
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define <4 x i32> @in_constant_42_vary(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) {
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; CHECK-LABEL: in_constant_42_vary:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v0.4s, #42
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; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
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; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%n0 = xor <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %y ; %x
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%n1 = and <4 x i32> %n0, %mask
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%r = xor <4 x i32> %n1, %y
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ret <4 x i32> %r
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}
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; This is not a canonical form. Testing for completeness only.
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define <4 x i32> @out_constant_42_vary_invmask(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) {
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; CHECK-LABEL: out_constant_42_vary_invmask:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: movi v2.4s, #42
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; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
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; CHECK-NEXT: ret
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%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
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%mx = and <4 x i32> %notmask, <i32 42, i32 42, i32 42, i32 42>
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%my = and <4 x i32> %mask, %y
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%r = or <4 x i32> %mx, %my
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ret <4 x i32> %r
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}
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; This is not a canonical form. Testing for completeness only.
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define <4 x i32> @in_constant_42_vary_invmask(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) {
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; CHECK-LABEL: in_constant_42_vary_invmask:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v0.4s, #42
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; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
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; CHECK-NEXT: bic v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
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%n0 = xor <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %y ; %x
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%n1 = and <4 x i32> %n0, %notmask
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%r = xor <4 x i32> %n1, %y
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ret <4 x i32> %r
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}
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@ -0,0 +1,466 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
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; https://bugs.llvm.org/show_bug.cgi?id=37104
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; All the advanced stuff (negative tests, commutativity) is handled in the
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; scalar version of the test only.
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; ============================================================================ ;
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; 8-bit vector width
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; ============================================================================ ;
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define <1 x i8> @out_v1i8(<1 x i8> %x, <1 x i8> %y, <1 x i8> %mask) nounwind {
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; CHECK-LABEL: out_v1i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: ret
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%mx = and <1 x i8> %x, %mask
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%notmask = xor <1 x i8> %mask, <i8 -1>
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%my = and <1 x i8> %y, %notmask
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%r = or <1 x i8> %mx, %my
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ret <1 x i8> %r
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}
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; ============================================================================ ;
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; 16-bit vector width
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; ============================================================================ ;
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define <2 x i8> @out_v2i8(<2 x i8> %x, <2 x i8> %y, <2 x i8> %mask) nounwind {
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; CHECK-LABEL: out_v2i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi d3, #0x0000ff000000ff
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; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
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; CHECK-NEXT: eor v2.8b, v2.8b, v3.8b
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; CHECK-NEXT: and v1.8b, v1.8b, v2.8b
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; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: ret
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%mx = and <2 x i8> %x, %mask
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%notmask = xor <2 x i8> %mask, <i8 -1, i8 -1>
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%my = and <2 x i8> %y, %notmask
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%r = or <2 x i8> %mx, %my
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ret <2 x i8> %r
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}
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define <1 x i16> @out_v1i16(<1 x i16> %x, <1 x i16> %y, <1 x i16> %mask) nounwind {
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; CHECK-LABEL: out_v1i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: ret
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%mx = and <1 x i16> %x, %mask
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%notmask = xor <1 x i16> %mask, <i16 -1>
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%my = and <1 x i16> %y, %notmask
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%r = or <1 x i16> %mx, %my
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ret <1 x i16> %r
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}
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; ============================================================================ ;
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; 32-bit vector width
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; ============================================================================ ;
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define <4 x i8> @out_v4i8(<4 x i8> %x, <4 x i8> %y, <4 x i8> %mask) nounwind {
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; CHECK-LABEL: out_v4i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi d3, #0xff00ff00ff00ff
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; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
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; CHECK-NEXT: eor v2.8b, v2.8b, v3.8b
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; CHECK-NEXT: and v1.8b, v1.8b, v2.8b
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; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: ret
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%mx = and <4 x i8> %x, %mask
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%notmask = xor <4 x i8> %mask, <i8 -1, i8 -1, i8 -1, i8 -1>
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%my = and <4 x i8> %y, %notmask
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%r = or <4 x i8> %mx, %my
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ret <4 x i8> %r
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}
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|
||||
define <4 x i8> @out_v4i8_undef(<4 x i8> %x, <4 x i8> %y, <4 x i8> %mask) nounwind {
|
||||
; CHECK-LABEL: out_v4i8_undef:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: movi d3, #0xff00ff00ff00ff
|
||||
; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
|
||||
; CHECK-NEXT: eor v2.8b, v2.8b, v3.8b
|
||||
; CHECK-NEXT: and v1.8b, v1.8b, v2.8b
|
||||
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: ret
|
||||
%mx = and <4 x i8> %x, %mask
|
||||
%notmask = xor <4 x i8> %mask, <i8 -1, i8 -1, i8 undef, i8 -1>
|
||||
%my = and <4 x i8> %y, %notmask
|
||||
%r = or <4 x i8> %mx, %my
|
||||
ret <4 x i8> %r
|
||||
}
|
||||
|
||||
define <2 x i16> @out_v2i16(<2 x i16> %x, <2 x i16> %y, <2 x i16> %mask) nounwind {
|
||||
; CHECK-LABEL: out_v2i16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: movi d3, #0x00ffff0000ffff
|
||||
; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
|
||||
; CHECK-NEXT: eor v2.8b, v2.8b, v3.8b
|
||||
; CHECK-NEXT: and v1.8b, v1.8b, v2.8b
|
||||
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: ret
|
||||
%mx = and <2 x i16> %x, %mask
|
||||
%notmask = xor <2 x i16> %mask, <i16 -1, i16 -1>
|
||||
%my = and <2 x i16> %y, %notmask
|
||||
%r = or <2 x i16> %mx, %my
|
||||
ret <2 x i16> %r
|
||||
}
|
||||
|
||||
define <1 x i32> @out_v1i32(<1 x i32> %x, <1 x i32> %y, <1 x i32> %mask) nounwind {
|
||||
; CHECK-LABEL: out_v1i32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: mov v0.16b, v2.16b
|
||||
; CHECK-NEXT: ret
|
||||
%mx = and <1 x i32> %x, %mask
|
||||
%notmask = xor <1 x i32> %mask, <i32 -1>
|
||||
%my = and <1 x i32> %y, %notmask
|
||||
%r = or <1 x i32> %mx, %my
|
||||
ret <1 x i32> %r
|
||||
}
|
||||
|
||||
; ============================================================================ ;
|
||||
; 64-bit vector width
|
||||
; ============================================================================ ;
|
||||
|
||||
define <8 x i8> @out_v8i8(<8 x i8> %x, <8 x i8> %y, <8 x i8> %mask) nounwind {
|
||||
; CHECK-LABEL: out_v8i8:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: mov v0.16b, v2.16b
|
||||
; CHECK-NEXT: ret
|
||||
%mx = and <8 x i8> %x, %mask
|
||||
%notmask = xor <8 x i8> %mask, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
|
||||
%my = and <8 x i8> %y, %notmask
|
||||
%r = or <8 x i8> %mx, %my
|
||||
ret <8 x i8> %r
|
||||
}
|
||||
|
||||
define <4 x i16> @out_v4i16(<4 x i16> %x, <4 x i16> %y, <4 x i16> %mask) nounwind {
|
||||
; CHECK-LABEL: out_v4i16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: mov v0.16b, v2.16b
|
||||
; CHECK-NEXT: ret
|
||||
%mx = and <4 x i16> %x, %mask
|
||||
%notmask = xor <4 x i16> %mask, <i16 -1, i16 -1, i16 -1, i16 -1>
|
||||
%my = and <4 x i16> %y, %notmask
|
||||
%r = or <4 x i16> %mx, %my
|
||||
ret <4 x i16> %r
|
||||
}
|
||||
|
||||
define <4 x i16> @out_v4i16_undef(<4 x i16> %x, <4 x i16> %y, <4 x i16> %mask) nounwind {
|
||||
; CHECK-LABEL: out_v4i16_undef:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: mov v0.16b, v2.16b
|
||||
; CHECK-NEXT: ret
|
||||
%mx = and <4 x i16> %x, %mask
|
||||
%notmask = xor <4 x i16> %mask, <i16 -1, i16 -1, i16 undef, i16 -1>
|
||||
%my = and <4 x i16> %y, %notmask
|
||||
%r = or <4 x i16> %mx, %my
|
||||
ret <4 x i16> %r
|
||||
}
|
||||
|
||||
define <2 x i32> @out_v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %mask) nounwind {
|
||||
; CHECK-LABEL: out_v2i32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: mov v0.16b, v2.16b
|
||||
; CHECK-NEXT: ret
|
||||
%mx = and <2 x i32> %x, %mask
|
||||
%notmask = xor <2 x i32> %mask, <i32 -1, i32 -1>
|
||||
%my = and <2 x i32> %y, %notmask
|
||||
%r = or <2 x i32> %mx, %my
|
||||
ret <2 x i32> %r
|
||||
}
|
||||
|
||||
define <1 x i64> @out_v1i64(<1 x i64> %x, <1 x i64> %y, <1 x i64> %mask) nounwind {
|
||||
; CHECK-LABEL: out_v1i64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: mov v0.16b, v2.16b
|
||||
; CHECK-NEXT: ret
|
||||
%mx = and <1 x i64> %x, %mask
|
||||
%notmask = xor <1 x i64> %mask, <i64 -1>
|
||||
%my = and <1 x i64> %y, %notmask
|
||||
%r = or <1 x i64> %mx, %my
|
||||
ret <1 x i64> %r
|
||||
}
|
||||
|
||||
; ============================================================================ ;
|
||||
; 128-bit vector width
|
||||
; ============================================================================ ;
|
||||
|
||||
define <16 x i8> @out_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %mask) nounwind {
|
||||
; CHECK-LABEL: out_v16i8:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b
|
||||
; CHECK-NEXT: mov v0.16b, v2.16b
|
||||
; CHECK-NEXT: ret
|
||||
%mx = and <16 x i8> %x, %mask
|
||||
%notmask = xor <16 x i8> %mask, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
|
||||
%my = and <16 x i8> %y, %notmask
|
||||
%r = or <16 x i8> %mx, %my
|
||||
ret <16 x i8> %r
|
||||
}
|
||||
|
||||
define <8 x i16> @out_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %mask) nounwind {
|
||||
; CHECK-LABEL: out_v8i16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b
|
||||
; CHECK-NEXT: mov v0.16b, v2.16b
|
||||
; CHECK-NEXT: ret
|
||||
%mx = and <8 x i16> %x, %mask
|
||||
%notmask = xor <8 x i16> %mask, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
|
||||
%my = and <8 x i16> %y, %notmask
|
||||
%r = or <8 x i16> %mx, %my
|
||||
ret <8 x i16> %r
|
||||
}
|
||||
|
||||
define <4 x i32> @out_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) nounwind {
|
||||
; CHECK-LABEL: out_v4i32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b
|
||||
; CHECK-NEXT: mov v0.16b, v2.16b
|
||||
; CHECK-NEXT: ret
|
||||
%mx = and <4 x i32> %x, %mask
|
||||
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
|
||||
%my = and <4 x i32> %y, %notmask
|
||||
%r = or <4 x i32> %mx, %my
|
||||
ret <4 x i32> %r
|
||||
}
|
||||
|
||||
define <4 x i32> @out_v4i32_undef(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) nounwind {
|
||||
; CHECK-LABEL: out_v4i32_undef:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b
|
||||
; CHECK-NEXT: mov v0.16b, v2.16b
|
||||
; CHECK-NEXT: ret
|
||||
%mx = and <4 x i32> %x, %mask
|
||||
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 undef, i32 -1>
|
||||
%my = and <4 x i32> %y, %notmask
|
||||
%r = or <4 x i32> %mx, %my
|
||||
ret <4 x i32> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @out_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %mask) nounwind {
|
||||
; CHECK-LABEL: out_v2i64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b
|
||||
; CHECK-NEXT: mov v0.16b, v2.16b
|
||||
; CHECK-NEXT: ret
|
||||
%mx = and <2 x i64> %x, %mask
|
||||
%notmask = xor <2 x i64> %mask, <i64 -1, i64 -1>
|
||||
%my = and <2 x i64> %y, %notmask
|
||||
%r = or <2 x i64> %mx, %my
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
; Should be the same as the previous one.
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
; ============================================================================ ;
|
||||
; 8-bit vector width
|
||||
; ============================================================================ ;
|
||||
|
||||
define <1 x i8> @in_v1i8(<1 x i8> %x, <1 x i8> %y, <1 x i8> %mask) nounwind {
|
||||
; CHECK-LABEL: in_v1i8:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
|
||||
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: ret
|
||||
%n0 = xor <1 x i8> %x, %y
|
||||
%n1 = and <1 x i8> %n0, %mask
|
||||
%r = xor <1 x i8> %n1, %y
|
||||
ret <1 x i8> %r
|
||||
}
|
||||
|
||||
; ============================================================================ ;
|
||||
; 16-bit vector width
|
||||
; ============================================================================ ;
|
||||
|
||||
define <2 x i8> @in_v2i8(<2 x i8> %x, <2 x i8> %y, <2 x i8> %mask) nounwind {
|
||||
; CHECK-LABEL: in_v2i8:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
|
||||
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: ret
|
||||
%n0 = xor <2 x i8> %x, %y
|
||||
%n1 = and <2 x i8> %n0, %mask
|
||||
%r = xor <2 x i8> %n1, %y
|
||||
ret <2 x i8> %r
|
||||
}
|
||||
|
||||
define <1 x i16> @in_v1i16(<1 x i16> %x, <1 x i16> %y, <1 x i16> %mask) nounwind {
|
||||
; CHECK-LABEL: in_v1i16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
|
||||
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: ret
|
||||
%n0 = xor <1 x i16> %x, %y
|
||||
%n1 = and <1 x i16> %n0, %mask
|
||||
%r = xor <1 x i16> %n1, %y
|
||||
ret <1 x i16> %r
|
||||
}
|
||||
|
||||
; ============================================================================ ;
|
||||
; 32-bit vector width
|
||||
; ============================================================================ ;
|
||||
|
||||
define <4 x i8> @in_v4i8(<4 x i8> %x, <4 x i8> %y, <4 x i8> %mask) nounwind {
|
||||
; CHECK-LABEL: in_v4i8:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
|
||||
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: ret
|
||||
%n0 = xor <4 x i8> %x, %y
|
||||
%n1 = and <4 x i8> %n0, %mask
|
||||
%r = xor <4 x i8> %n1, %y
|
||||
ret <4 x i8> %r
|
||||
}
|
||||
|
||||
define <2 x i16> @in_v2i16(<2 x i16> %x, <2 x i16> %y, <2 x i16> %mask) nounwind {
|
||||
; CHECK-LABEL: in_v2i16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
|
||||
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: ret
|
||||
%n0 = xor <2 x i16> %x, %y
|
||||
%n1 = and <2 x i16> %n0, %mask
|
||||
%r = xor <2 x i16> %n1, %y
|
||||
ret <2 x i16> %r
|
||||
}
|
||||
|
||||
define <1 x i32> @in_v1i32(<1 x i32> %x, <1 x i32> %y, <1 x i32> %mask) nounwind {
|
||||
; CHECK-LABEL: in_v1i32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
|
||||
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: ret
|
||||
%n0 = xor <1 x i32> %x, %y
|
||||
%n1 = and <1 x i32> %n0, %mask
|
||||
%r = xor <1 x i32> %n1, %y
|
||||
ret <1 x i32> %r
|
||||
}
|
||||
|
||||
; ============================================================================ ;
|
||||
; 64-bit vector width
|
||||
; ============================================================================ ;
|
||||
|
||||
define <8 x i8> @in_v8i8(<8 x i8> %x, <8 x i8> %y, <8 x i8> %mask) nounwind {
|
||||
; CHECK-LABEL: in_v8i8:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
|
||||
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: ret
|
||||
%n0 = xor <8 x i8> %x, %y
|
||||
%n1 = and <8 x i8> %n0, %mask
|
||||
%r = xor <8 x i8> %n1, %y
|
||||
ret <8 x i8> %r
|
||||
}
|
||||
|
||||
define <4 x i16> @in_v4i16(<4 x i16> %x, <4 x i16> %y, <4 x i16> %mask) nounwind {
|
||||
; CHECK-LABEL: in_v4i16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
|
||||
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: ret
|
||||
%n0 = xor <4 x i16> %x, %y
|
||||
%n1 = and <4 x i16> %n0, %mask
|
||||
%r = xor <4 x i16> %n1, %y
|
||||
ret <4 x i16> %r
|
||||
}
|
||||
|
||||
define <2 x i32> @in_v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %mask) nounwind {
|
||||
; CHECK-LABEL: in_v2i32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
|
||||
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: ret
|
||||
%n0 = xor <2 x i32> %x, %y
|
||||
%n1 = and <2 x i32> %n0, %mask
|
||||
%r = xor <2 x i32> %n1, %y
|
||||
ret <2 x i32> %r
|
||||
}
|
||||
|
||||
define <1 x i64> @in_v1i64(<1 x i64> %x, <1 x i64> %y, <1 x i64> %mask) nounwind {
|
||||
; CHECK-LABEL: in_v1i64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
|
||||
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: ret
|
||||
%n0 = xor <1 x i64> %x, %y
|
||||
%n1 = and <1 x i64> %n0, %mask
|
||||
%r = xor <1 x i64> %n1, %y
|
||||
ret <1 x i64> %r
|
||||
}
|
||||
|
||||
; ============================================================================ ;
|
||||
; 128-bit vector width
|
||||
; ============================================================================ ;
|
||||
|
||||
define <16 x i8> @in_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %mask) nounwind {
|
||||
; CHECK-LABEL: in_v16i8:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
|
||||
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
|
||||
; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
|
||||
; CHECK-NEXT: ret
|
||||
%n0 = xor <16 x i8> %x, %y
|
||||
%n1 = and <16 x i8> %n0, %mask
|
||||
%r = xor <16 x i8> %n1, %y
|
||||
ret <16 x i8> %r
|
||||
}
|
||||
|
||||
define <8 x i16> @in_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %mask) nounwind {
|
||||
; CHECK-LABEL: in_v8i16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
|
||||
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
|
||||
; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
|
||||
; CHECK-NEXT: ret
|
||||
%n0 = xor <8 x i16> %x, %y
|
||||
%n1 = and <8 x i16> %n0, %mask
|
||||
%r = xor <8 x i16> %n1, %y
|
||||
ret <8 x i16> %r
|
||||
}
|
||||
|
||||
define <4 x i32> @in_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) nounwind {
|
||||
; CHECK-LABEL: in_v4i32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
|
||||
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
|
||||
; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
|
||||
; CHECK-NEXT: ret
|
||||
%n0 = xor <4 x i32> %x, %y
|
||||
%n1 = and <4 x i32> %n0, %mask
|
||||
%r = xor <4 x i32> %n1, %y
|
||||
ret <4 x i32> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @in_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %mask) nounwind {
|
||||
; CHECK-LABEL: in_v2i64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
|
||||
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
|
||||
; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
|
||||
; CHECK-NEXT: ret
|
||||
%n0 = xor <2 x i64> %x, %y
|
||||
%n1 = and <2 x i64> %n0, %mask
|
||||
%r = xor <2 x i64> %n1, %y
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
|
@ -10,7 +10,7 @@ define i32 @t1(i32 %a, i32 %b) nounwind {
|
|||
; CHECK-NEXT: testl %esi, %esi
|
||||
; CHECK-NEXT: je LBB0_1
|
||||
; CHECK-NEXT: ## %bb.2: ## %while.body.preheader
|
||||
; CHECK-NEXT: movl %esi, %edx
|
||||
; CHECK-NEXT: movl %esi, %edx
|
||||
; CHECK-NEXT: .p2align 4, 0x90
|
||||
; CHECK-NEXT: LBB0_3: ## %while.body
|
||||
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
|
||||
|
|
|
|||
|
|
@ -0,0 +1,618 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+sse,-sse2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SSE,CHECK-SSE1
|
||||
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+sse,+sse2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SSE,CHECK-SSE2
|
||||
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+xop < %s | FileCheck %s --check-prefixes=CHECK,CHECK-XOP
|
||||
|
||||
; ============================================================================ ;
|
||||
; Various cases with %x and/or %y being a constant
|
||||
; ============================================================================ ;
|
||||
|
||||
define <4 x i32> @out_constant_varx_mone(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
|
||||
; CHECK-SSE1-LABEL: out_constant_varx_mone:
|
||||
; CHECK-SSE1: # %bb.0:
|
||||
; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
|
||||
; CHECK-SSE1-NEXT: movaps {{.*#+}} xmm1 = [nan,nan,nan,nan]
|
||||
; CHECK-SSE1-NEXT: xorps %xmm0, %xmm1
|
||||
; CHECK-SSE1-NEXT: andps (%rsi), %xmm0
|
||||
; CHECK-SSE1-NEXT: orps %xmm1, %xmm0
|
||||
; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
|
||||
; CHECK-SSE1-NEXT: movq %rdi, %rax
|
||||
; CHECK-SSE1-NEXT: retq
|
||||
;
|
||||
; CHECK-SSE2-LABEL: out_constant_varx_mone:
|
||||
; CHECK-SSE2: # %bb.0:
|
||||
; CHECK-SSE2-NEXT: movdqa (%rdx), %xmm0
|
||||
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm1
|
||||
; CHECK-SSE2-NEXT: pxor %xmm0, %xmm1
|
||||
; CHECK-SSE2-NEXT: pand (%rdi), %xmm0
|
||||
; CHECK-SSE2-NEXT: por %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: retq
|
||||
;
|
||||
; CHECK-XOP-LABEL: out_constant_varx_mone:
|
||||
; CHECK-XOP: # %bb.0:
|
||||
; CHECK-XOP-NEXT: vmovdqa (%rdx), %xmm0
|
||||
; CHECK-XOP-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
|
||||
; CHECK-XOP-NEXT: vpxor %xmm1, %xmm0, %xmm1
|
||||
; CHECK-XOP-NEXT: vpand (%rdi), %xmm0, %xmm0
|
||||
; CHECK-XOP-NEXT: vpor %xmm1, %xmm0, %xmm0
|
||||
; CHECK-XOP-NEXT: retq
|
||||
%x = load <4 x i32>, <4 x i32> *%px, align 16
|
||||
%y = load <4 x i32>, <4 x i32> *%py, align 16
|
||||
%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
|
||||
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
|
||||
%mx = and <4 x i32> %mask, %x
|
||||
%my = and <4 x i32> %notmask, <i32 -1, i32 -1, i32 -1, i32 -1>
|
||||
%r = or <4 x i32> %mx, %my
|
||||
ret <4 x i32> %r
|
||||
}
|
||||
|
||||
define <4 x i32> @in_constant_varx_mone(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
|
||||
; CHECK-SSE1-LABEL: in_constant_varx_mone:
|
||||
; CHECK-SSE1: # %bb.0:
|
||||
; CHECK-SSE1-NEXT: movaps (%rsi), %xmm0
|
||||
; CHECK-SSE1-NEXT: andnps (%rcx), %xmm0
|
||||
; CHECK-SSE1-NEXT: xorps {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
|
||||
; CHECK-SSE1-NEXT: movq %rdi, %rax
|
||||
; CHECK-SSE1-NEXT: retq
|
||||
;
|
||||
; CHECK-SSE2-LABEL: in_constant_varx_mone:
|
||||
; CHECK-SSE2: # %bb.0:
|
||||
; CHECK-SSE2-NEXT: movdqa (%rdi), %xmm0
|
||||
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm1
|
||||
; CHECK-SSE2-NEXT: pandn (%rdx), %xmm0
|
||||
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: retq
|
||||
;
|
||||
; CHECK-XOP-LABEL: in_constant_varx_mone:
|
||||
; CHECK-XOP: # %bb.0:
|
||||
; CHECK-XOP-NEXT: vmovdqa (%rdi), %xmm0
|
||||
; CHECK-XOP-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
|
||||
; CHECK-XOP-NEXT: vpandn (%rdx), %xmm0, %xmm0
|
||||
; CHECK-XOP-NEXT: vpxor %xmm1, %xmm0, %xmm0
|
||||
; CHECK-XOP-NEXT: retq
|
||||
%x = load <4 x i32>, <4 x i32> *%px, align 16
|
||||
%y = load <4 x i32>, <4 x i32> *%py, align 16
|
||||
%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
|
||||
%n0 = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> ; %x
|
||||
%n1 = and <4 x i32> %n0, %mask
|
||||
%r = xor <4 x i32> %n1, <i32 -1, i32 -1, i32 -1, i32 -1>
|
||||
ret <4 x i32> %r
|
||||
}
|
||||
|
||||
; This is not a canonical form. Testing for completeness only.
|
||||
define <4 x i32> @out_constant_varx_mone_invmask(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
|
||||
; CHECK-SSE1-LABEL: out_constant_varx_mone_invmask:
|
||||
; CHECK-SSE1: # %bb.0:
|
||||
; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
|
||||
; CHECK-SSE1-NEXT: movaps %xmm0, %xmm1
|
||||
; CHECK-SSE1-NEXT: andnps (%rsi), %xmm1
|
||||
; CHECK-SSE1-NEXT: orps %xmm0, %xmm1
|
||||
; CHECK-SSE1-NEXT: movaps %xmm1, (%rdi)
|
||||
; CHECK-SSE1-NEXT: movq %rdi, %rax
|
||||
; CHECK-SSE1-NEXT: retq
|
||||
;
|
||||
; CHECK-SSE2-LABEL: out_constant_varx_mone_invmask:
|
||||
; CHECK-SSE2: # %bb.0:
|
||||
; CHECK-SSE2-NEXT: movaps (%rdx), %xmm1
|
||||
; CHECK-SSE2-NEXT: movaps %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: andnps (%rdi), %xmm0
|
||||
; CHECK-SSE2-NEXT: orps %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: retq
|
||||
;
|
||||
; CHECK-XOP-LABEL: out_constant_varx_mone_invmask:
|
||||
; CHECK-XOP: # %bb.0:
|
||||
; CHECK-XOP-NEXT: vmovaps (%rdx), %xmm0
|
||||
; CHECK-XOP-NEXT: vandnps (%rdi), %xmm0, %xmm1
|
||||
; CHECK-XOP-NEXT: vorps %xmm0, %xmm1, %xmm0
|
||||
; CHECK-XOP-NEXT: retq
|
||||
%x = load <4 x i32>, <4 x i32> *%px, align 16
|
||||
%y = load <4 x i32>, <4 x i32> *%py, align 16
|
||||
%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
|
||||
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
|
||||
%mx = and <4 x i32> %notmask, %x
|
||||
%my = and <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
|
||||
%r = or <4 x i32> %mx, %my
|
||||
ret <4 x i32> %r
|
||||
}
|
||||
|
||||
; This is not a canonical form. Testing for completeness only.
|
||||
define <4 x i32> @in_constant_varx_mone_invmask(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
|
||||
; CHECK-SSE1-LABEL: in_constant_varx_mone_invmask:
|
||||
; CHECK-SSE1: # %bb.0:
|
||||
; CHECK-SSE1-NEXT: movaps (%rsi), %xmm0
|
||||
; CHECK-SSE1-NEXT: movaps {{.*#+}} xmm1 = [nan,nan,nan,nan]
|
||||
; CHECK-SSE1-NEXT: movaps (%rcx), %xmm2
|
||||
; CHECK-SSE1-NEXT: xorps %xmm1, %xmm2
|
||||
; CHECK-SSE1-NEXT: andnps %xmm2, %xmm0
|
||||
; CHECK-SSE1-NEXT: xorps %xmm1, %xmm0
|
||||
; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
|
||||
; CHECK-SSE1-NEXT: movq %rdi, %rax
|
||||
; CHECK-SSE1-NEXT: retq
|
||||
;
|
||||
; CHECK-SSE2-LABEL: in_constant_varx_mone_invmask:
|
||||
; CHECK-SSE2: # %bb.0:
|
||||
; CHECK-SSE2-NEXT: movdqa (%rdi), %xmm0
|
||||
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm1
|
||||
; CHECK-SSE2-NEXT: movdqa (%rdx), %xmm2
|
||||
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm2
|
||||
; CHECK-SSE2-NEXT: pandn %xmm2, %xmm0
|
||||
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: retq
|
||||
;
|
||||
; CHECK-XOP-LABEL: in_constant_varx_mone_invmask:
|
||||
; CHECK-XOP: # %bb.0:
|
||||
; CHECK-XOP-NEXT: vmovdqa (%rdi), %xmm0
|
||||
; CHECK-XOP-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
|
||||
; CHECK-XOP-NEXT: vpxor (%rdx), %xmm1, %xmm2
|
||||
; CHECK-XOP-NEXT: vpandn %xmm2, %xmm0, %xmm0
|
||||
; CHECK-XOP-NEXT: vpxor %xmm1, %xmm0, %xmm0
|
||||
; CHECK-XOP-NEXT: retq
|
||||
%x = load <4 x i32>, <4 x i32> *%px, align 16
|
||||
%y = load <4 x i32>, <4 x i32> *%py, align 16
|
||||
%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
|
||||
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
|
||||
%n0 = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> ; %x
|
||||
%n1 = and <4 x i32> %n0, %notmask
|
||||
%r = xor <4 x i32> %n1, <i32 -1, i32 -1, i32 -1, i32 -1>
|
||||
ret <4 x i32> %r
|
||||
}
|
||||
|
||||
define <4 x i32> @out_constant_varx_42(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
|
||||
; CHECK-SSE1-LABEL: out_constant_varx_42:
|
||||
; CHECK-SSE1: # %bb.0:
|
||||
; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
|
||||
; CHECK-SSE1-NEXT: movaps (%rsi), %xmm1
|
||||
; CHECK-SSE1-NEXT: andps %xmm0, %xmm1
|
||||
; CHECK-SSE1-NEXT: andnps {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE1-NEXT: orps %xmm1, %xmm0
|
||||
; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
|
||||
; CHECK-SSE1-NEXT: movq %rdi, %rax
|
||||
; CHECK-SSE1-NEXT: retq
|
||||
;
|
||||
; CHECK-SSE2-LABEL: out_constant_varx_42:
|
||||
; CHECK-SSE2: # %bb.0:
|
||||
; CHECK-SSE2-NEXT: movaps (%rdx), %xmm0
|
||||
; CHECK-SSE2-NEXT: movaps (%rdi), %xmm1
|
||||
; CHECK-SSE2-NEXT: andps %xmm0, %xmm1
|
||||
; CHECK-SSE2-NEXT: andnps {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE2-NEXT: orps %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: retq
|
||||
;
|
||||
; CHECK-XOP-LABEL: out_constant_varx_42:
|
||||
; CHECK-XOP: # %bb.0:
|
||||
; CHECK-XOP-NEXT: vmovdqa (%rdi), %xmm0
|
||||
; CHECK-XOP-NEXT: vmovdqa (%rdx), %xmm1
|
||||
; CHECK-XOP-NEXT: vpcmov %xmm1, {{.*}}(%rip), %xmm0, %xmm0
|
||||
; CHECK-XOP-NEXT: retq
|
||||
%x = load <4 x i32>, <4 x i32> *%px, align 16
|
||||
%y = load <4 x i32>, <4 x i32> *%py, align 16
|
||||
%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
|
||||
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
|
||||
%mx = and <4 x i32> %mask, %x
|
||||
%my = and <4 x i32> %notmask, <i32 42, i32 42, i32 42, i32 42>
|
||||
%r = or <4 x i32> %mx, %my
|
||||
ret <4 x i32> %r
|
||||
}
|
||||
|
||||
define <4 x i32> @in_constant_varx_42(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
|
||||
; CHECK-SSE1-LABEL: in_constant_varx_42:
|
||||
; CHECK-SSE1: # %bb.0:
|
||||
; CHECK-SSE1-NEXT: movaps {{.*#+}} xmm0 = [5.885454e-44,5.885454e-44,5.885454e-44,5.885454e-44]
|
||||
; CHECK-SSE1-NEXT: movaps (%rsi), %xmm1
|
||||
; CHECK-SSE1-NEXT: xorps %xmm0, %xmm1
|
||||
; CHECK-SSE1-NEXT: andps (%rcx), %xmm1
|
||||
; CHECK-SSE1-NEXT: xorps %xmm0, %xmm1
|
||||
; CHECK-SSE1-NEXT: movaps %xmm1, (%rdi)
|
||||
; CHECK-SSE1-NEXT: movq %rdi, %rax
|
||||
; CHECK-SSE1-NEXT: retq
|
||||
;
|
||||
; CHECK-SSE2-LABEL: in_constant_varx_42:
|
||||
; CHECK-SSE2: # %bb.0:
|
||||
; CHECK-SSE2-NEXT: movaps {{.*#+}} xmm1 = [42,42,42,42]
|
||||
; CHECK-SSE2-NEXT: movaps (%rdi), %xmm0
|
||||
; CHECK-SSE2-NEXT: xorps %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: andps (%rdx), %xmm0
|
||||
; CHECK-SSE2-NEXT: xorps %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: retq
|
||||
;
|
||||
; CHECK-XOP-LABEL: in_constant_varx_42:
|
||||
; CHECK-XOP: # %bb.0:
|
||||
; CHECK-XOP-NEXT: vmovaps {{.*#+}} xmm0 = [42,42,42,42]
|
||||
; CHECK-XOP-NEXT: vxorps (%rdi), %xmm0, %xmm1
|
||||
; CHECK-XOP-NEXT: vandps (%rdx), %xmm1, %xmm1
|
||||
; CHECK-XOP-NEXT: vxorps %xmm0, %xmm1, %xmm0
|
||||
; CHECK-XOP-NEXT: retq
|
||||
%x = load <4 x i32>, <4 x i32> *%px, align 16
|
||||
%y = load <4 x i32>, <4 x i32> *%py, align 16
|
||||
%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
|
||||
%n0 = xor <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42> ; %x
|
||||
%n1 = and <4 x i32> %n0, %mask
|
||||
%r = xor <4 x i32> %n1, <i32 42, i32 42, i32 42, i32 42>
|
||||
ret <4 x i32> %r
|
||||
}
|
||||
|
||||
; This is not a canonical form. Testing for completeness only.
|
||||
define <4 x i32> @out_constant_varx_42_invmask(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
|
||||
; CHECK-SSE1-LABEL: out_constant_varx_42_invmask:
|
||||
; CHECK-SSE1: # %bb.0:
|
||||
; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
|
||||
; CHECK-SSE1-NEXT: movaps %xmm0, %xmm1
|
||||
; CHECK-SSE1-NEXT: andnps (%rsi), %xmm1
|
||||
; CHECK-SSE1-NEXT: andps {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE1-NEXT: orps %xmm1, %xmm0
|
||||
; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
|
||||
; CHECK-SSE1-NEXT: movq %rdi, %rax
|
||||
; CHECK-SSE1-NEXT: retq
|
||||
;
|
||||
; CHECK-SSE2-LABEL: out_constant_varx_42_invmask:
|
||||
; CHECK-SSE2: # %bb.0:
|
||||
; CHECK-SSE2-NEXT: movaps (%rdx), %xmm0
|
||||
; CHECK-SSE2-NEXT: movaps %xmm0, %xmm1
|
||||
; CHECK-SSE2-NEXT: andnps (%rdi), %xmm1
|
||||
; CHECK-SSE2-NEXT: andps {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE2-NEXT: orps %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: retq
|
||||
;
|
||||
; CHECK-XOP-LABEL: out_constant_varx_42_invmask:
|
||||
; CHECK-XOP: # %bb.0:
|
||||
; CHECK-XOP-NEXT: vmovdqa (%rdx), %xmm0
|
||||
; CHECK-XOP-NEXT: vmovdqa {{.*#+}} xmm1 = [42,42,42,42]
|
||||
; CHECK-XOP-NEXT: vpcmov %xmm0, (%rdi), %xmm1, %xmm0
|
||||
; CHECK-XOP-NEXT: retq
|
||||
%x = load <4 x i32>, <4 x i32> *%px, align 16
|
||||
%y = load <4 x i32>, <4 x i32> *%py, align 16
|
||||
%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
|
||||
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
|
||||
%mx = and <4 x i32> %notmask, %x
|
||||
%my = and <4 x i32> %mask, <i32 42, i32 42, i32 42, i32 42>
|
||||
%r = or <4 x i32> %mx, %my
|
||||
ret <4 x i32> %r
|
||||
}
|
||||
|
||||
; This is not a canonical form. Testing for completeness only.
|
||||
define <4 x i32> @in_constant_varx_42_invmask(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
|
||||
; CHECK-SSE1-LABEL: in_constant_varx_42_invmask:
|
||||
; CHECK-SSE1: # %bb.0:
|
||||
; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
|
||||
; CHECK-SSE1-NEXT: movaps {{.*#+}} xmm1 = [5.885454e-44,5.885454e-44,5.885454e-44,5.885454e-44]
|
||||
; CHECK-SSE1-NEXT: movaps (%rsi), %xmm2
|
||||
; CHECK-SSE1-NEXT: xorps %xmm1, %xmm2
|
||||
; CHECK-SSE1-NEXT: andnps %xmm2, %xmm0
|
||||
; CHECK-SSE1-NEXT: xorps %xmm1, %xmm0
|
||||
; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
|
||||
; CHECK-SSE1-NEXT: movq %rdi, %rax
|
||||
; CHECK-SSE1-NEXT: retq
|
||||
;
|
||||
; CHECK-SSE2-LABEL: in_constant_varx_42_invmask:
|
||||
; CHECK-SSE2: # %bb.0:
|
||||
; CHECK-SSE2-NEXT: movaps (%rdx), %xmm0
|
||||
; CHECK-SSE2-NEXT: movaps {{.*#+}} xmm1 = [42,42,42,42]
|
||||
; CHECK-SSE2-NEXT: movaps (%rdi), %xmm2
|
||||
; CHECK-SSE2-NEXT: xorps %xmm1, %xmm2
|
||||
; CHECK-SSE2-NEXT: andnps %xmm2, %xmm0
|
||||
; CHECK-SSE2-NEXT: xorps %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: retq
|
||||
;
|
||||
; CHECK-XOP-LABEL: in_constant_varx_42_invmask:
|
||||
; CHECK-XOP: # %bb.0:
|
||||
; CHECK-XOP-NEXT: vmovaps (%rdx), %xmm0
|
||||
; CHECK-XOP-NEXT: vmovaps {{.*#+}} xmm1 = [42,42,42,42]
|
||||
; CHECK-XOP-NEXT: vxorps (%rdi), %xmm1, %xmm2
|
||||
; CHECK-XOP-NEXT: vandnps %xmm2, %xmm0, %xmm0
|
||||
; CHECK-XOP-NEXT: vxorps %xmm1, %xmm0, %xmm0
|
||||
; CHECK-XOP-NEXT: retq
|
||||
%x = load <4 x i32>, <4 x i32> *%px, align 16
|
||||
%y = load <4 x i32>, <4 x i32> *%py, align 16
|
||||
%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
|
||||
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
|
||||
%n0 = xor <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42> ; %x
|
||||
%n1 = and <4 x i32> %n0, %notmask
|
||||
%r = xor <4 x i32> %n1, <i32 42, i32 42, i32 42, i32 42>
|
||||
ret <4 x i32> %r
|
||||
}
|
||||
|
||||
define <4 x i32> @out_constant_mone_vary(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
|
||||
; CHECK-SSE1-LABEL: out_constant_mone_vary:
|
||||
; CHECK-SSE1: # %bb.0:
|
||||
; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
|
||||
; CHECK-SSE1-NEXT: movaps %xmm0, %xmm1
|
||||
; CHECK-SSE1-NEXT: andnps (%rdx), %xmm1
|
||||
; CHECK-SSE1-NEXT: orps %xmm0, %xmm1
|
||||
; CHECK-SSE1-NEXT: movaps %xmm1, (%rdi)
|
||||
; CHECK-SSE1-NEXT: movq %rdi, %rax
|
||||
; CHECK-SSE1-NEXT: retq
|
||||
;
|
||||
; CHECK-SSE2-LABEL: out_constant_mone_vary:
|
||||
; CHECK-SSE2: # %bb.0:
|
||||
; CHECK-SSE2-NEXT: movaps (%rdx), %xmm1
|
||||
; CHECK-SSE2-NEXT: movaps %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: andnps (%rsi), %xmm0
|
||||
; CHECK-SSE2-NEXT: orps %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: retq
|
||||
;
|
||||
; CHECK-XOP-LABEL: out_constant_mone_vary:
|
||||
; CHECK-XOP: # %bb.0:
|
||||
; CHECK-XOP-NEXT: vmovaps (%rdx), %xmm0
|
||||
; CHECK-XOP-NEXT: vandnps (%rsi), %xmm0, %xmm1
|
||||
; CHECK-XOP-NEXT: vorps %xmm1, %xmm0, %xmm0
|
||||
; CHECK-XOP-NEXT: retq
|
||||
%x = load <4 x i32>, <4 x i32> *%px, align 16
|
||||
%y = load <4 x i32>, <4 x i32> *%py, align 16
|
||||
%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
|
||||
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
|
||||
%mx = and <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
|
||||
%my = and <4 x i32> %notmask, %y
|
||||
%r = or <4 x i32> %mx, %my
|
||||
ret <4 x i32> %r
|
||||
}
|
||||
|
||||
define <4 x i32> @in_constant_mone_vary(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
|
||||
; CHECK-SSE1-LABEL: in_constant_mone_vary:
|
||||
; CHECK-SSE1: # %bb.0:
|
||||
; CHECK-SSE1-NEXT: movaps (%rdx), %xmm0
|
||||
; CHECK-SSE1-NEXT: movaps %xmm0, %xmm1
|
||||
; CHECK-SSE1-NEXT: andnps (%rcx), %xmm1
|
||||
; CHECK-SSE1-NEXT: xorps %xmm0, %xmm1
|
||||
; CHECK-SSE1-NEXT: movaps %xmm1, (%rdi)
|
||||
; CHECK-SSE1-NEXT: movq %rdi, %rax
|
||||
; CHECK-SSE1-NEXT: retq
|
||||
;
|
||||
; CHECK-SSE2-LABEL: in_constant_mone_vary:
|
||||
; CHECK-SSE2: # %bb.0:
|
||||
; CHECK-SSE2-NEXT: movaps (%rsi), %xmm1
|
||||
; CHECK-SSE2-NEXT: movaps %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: andnps (%rdx), %xmm0
|
||||
; CHECK-SSE2-NEXT: xorps %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: retq
|
||||
;
|
||||
; CHECK-XOP-LABEL: in_constant_mone_vary:
|
||||
; CHECK-XOP: # %bb.0:
|
||||
; CHECK-XOP-NEXT: vmovaps (%rsi), %xmm0
|
||||
; CHECK-XOP-NEXT: vandnps (%rdx), %xmm0, %xmm1
|
||||
; CHECK-XOP-NEXT: vxorps %xmm0, %xmm1, %xmm0
|
||||
; CHECK-XOP-NEXT: retq
|
||||
%x = load <4 x i32>, <4 x i32> *%px, align 16
|
||||
%y = load <4 x i32>, <4 x i32> *%py, align 16
|
||||
%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
|
||||
%n0 = xor <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %y ; %x
|
||||
%n1 = and <4 x i32> %n0, %mask
|
||||
%r = xor <4 x i32> %n1, %y
|
||||
ret <4 x i32> %r
|
||||
}
|
||||
|
||||
; This is not a canonical form. Testing for completeness only.
|
||||
define <4 x i32> @out_constant_mone_vary_invmask(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
|
||||
; CHECK-SSE1-LABEL: out_constant_mone_vary_invmask:
|
||||
; CHECK-SSE1: # %bb.0:
|
||||
; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
|
||||
; CHECK-SSE1-NEXT: movaps {{.*#+}} xmm1 = [nan,nan,nan,nan]
|
||||
; CHECK-SSE1-NEXT: xorps %xmm0, %xmm1
|
||||
; CHECK-SSE1-NEXT: andps (%rdx), %xmm0
|
||||
; CHECK-SSE1-NEXT: orps %xmm1, %xmm0
|
||||
; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
|
||||
; CHECK-SSE1-NEXT: movq %rdi, %rax
|
||||
; CHECK-SSE1-NEXT: retq
|
||||
;
|
||||
; CHECK-SSE2-LABEL: out_constant_mone_vary_invmask:
|
||||
; CHECK-SSE2: # %bb.0:
|
||||
; CHECK-SSE2-NEXT: movdqa (%rdx), %xmm0
|
||||
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm1
|
||||
; CHECK-SSE2-NEXT: pxor %xmm0, %xmm1
|
||||
; CHECK-SSE2-NEXT: pand (%rsi), %xmm0
|
||||
; CHECK-SSE2-NEXT: por %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: retq
|
||||
;
|
||||
; CHECK-XOP-LABEL: out_constant_mone_vary_invmask:
|
||||
; CHECK-XOP: # %bb.0:
|
||||
; CHECK-XOP-NEXT: vmovdqa (%rdx), %xmm0
|
||||
; CHECK-XOP-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
|
||||
; CHECK-XOP-NEXT: vpxor %xmm1, %xmm0, %xmm1
|
||||
; CHECK-XOP-NEXT: vpand (%rsi), %xmm0, %xmm0
|
||||
; CHECK-XOP-NEXT: vpor %xmm0, %xmm1, %xmm0
|
||||
; CHECK-XOP-NEXT: retq
|
||||
%x = load <4 x i32>, <4 x i32> *%px, align 16
|
||||
%y = load <4 x i32>, <4 x i32> *%py, align 16
|
||||
%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
|
||||
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
|
||||
%mx = and <4 x i32> %notmask, <i32 -1, i32 -1, i32 -1, i32 -1>
|
||||
%my = and <4 x i32> %mask, %y
|
||||
%r = or <4 x i32> %mx, %my
|
||||
ret <4 x i32> %r
|
||||
}
|
||||
|
||||
; This is not a canonical form. Testing for completeness only.
|
||||
define <4 x i32> @in_constant_mone_vary_invmask(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
|
||||
; CHECK-SSE1-LABEL: in_constant_mone_vary_invmask:
|
||||
; CHECK-SSE1: # %bb.0:
|
||||
; CHECK-SSE1-NEXT: movaps (%rdx), %xmm0
|
||||
; CHECK-SSE1-NEXT: movaps (%rcx), %xmm1
|
||||
; CHECK-SSE1-NEXT: xorps {{.*}}(%rip), %xmm1
|
||||
; CHECK-SSE1-NEXT: movaps %xmm0, %xmm2
|
||||
; CHECK-SSE1-NEXT: andnps %xmm1, %xmm2
|
||||
; CHECK-SSE1-NEXT: xorps %xmm0, %xmm2
|
||||
; CHECK-SSE1-NEXT: movaps %xmm2, (%rdi)
|
||||
; CHECK-SSE1-NEXT: movq %rdi, %rax
|
||||
; CHECK-SSE1-NEXT: retq
|
||||
;
|
||||
; CHECK-SSE2-LABEL: in_constant_mone_vary_invmask:
|
||||
; CHECK-SSE2: # %bb.0:
|
||||
; CHECK-SSE2-NEXT: movdqa (%rsi), %xmm1
|
||||
; CHECK-SSE2-NEXT: pcmpeqd %xmm2, %xmm2
|
||||
; CHECK-SSE2-NEXT: pxor (%rdx), %xmm2
|
||||
; CHECK-SSE2-NEXT: movdqa %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: pandn %xmm2, %xmm0
|
||||
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: retq
|
||||
;
|
||||
; CHECK-XOP-LABEL: in_constant_mone_vary_invmask:
|
||||
; CHECK-XOP: # %bb.0:
|
||||
; CHECK-XOP-NEXT: vmovdqa (%rsi), %xmm0
|
||||
; CHECK-XOP-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
|
||||
; CHECK-XOP-NEXT: vpxor (%rdx), %xmm1, %xmm1
|
||||
; CHECK-XOP-NEXT: vpandn %xmm1, %xmm0, %xmm1
|
||||
; CHECK-XOP-NEXT: vpxor %xmm0, %xmm1, %xmm0
|
||||
; CHECK-XOP-NEXT: retq
|
||||
%x = load <4 x i32>, <4 x i32> *%px, align 16
|
||||
%y = load <4 x i32>, <4 x i32> *%py, align 16
|
||||
%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
|
||||
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
|
||||
%n0 = xor <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %y ; %x
|
||||
%n1 = and <4 x i32> %n0, %notmask
|
||||
%r = xor <4 x i32> %n1, %y
|
||||
ret <4 x i32> %r
|
||||
}
|
||||
|
||||
define <4 x i32> @out_constant_42_vary(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
|
||||
; CHECK-SSE1-LABEL: out_constant_42_vary:
|
||||
; CHECK-SSE1: # %bb.0:
|
||||
; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
|
||||
; CHECK-SSE1-NEXT: movaps {{.*#+}} xmm1 = [5.885454e-44,5.885454e-44,5.885454e-44,5.885454e-44]
|
||||
; CHECK-SSE1-NEXT: andps %xmm0, %xmm1
|
||||
; CHECK-SSE1-NEXT: andnps (%rdx), %xmm0
|
||||
; CHECK-SSE1-NEXT: orps %xmm1, %xmm0
|
||||
; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
|
||||
; CHECK-SSE1-NEXT: movq %rdi, %rax
|
||||
; CHECK-SSE1-NEXT: retq
|
||||
;
|
||||
; CHECK-SSE2-LABEL: out_constant_42_vary:
|
||||
; CHECK-SSE2: # %bb.0:
|
||||
; CHECK-SSE2-NEXT: movaps (%rdx), %xmm0
|
||||
; CHECK-SSE2-NEXT: movaps {{.*#+}} xmm1 = [42,42,42,42]
|
||||
; CHECK-SSE2-NEXT: andps %xmm0, %xmm1
|
||||
; CHECK-SSE2-NEXT: andnps (%rsi), %xmm0
|
||||
; CHECK-SSE2-NEXT: orps %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: retq
|
||||
;
|
||||
; CHECK-XOP-LABEL: out_constant_42_vary:
|
||||
; CHECK-XOP: # %bb.0:
|
||||
; CHECK-XOP-NEXT: vmovdqa (%rdx), %xmm0
|
||||
; CHECK-XOP-NEXT: vmovdqa {{.*#+}} xmm1 = [42,42,42,42]
|
||||
; CHECK-XOP-NEXT: vpcmov %xmm0, (%rsi), %xmm1, %xmm0
|
||||
; CHECK-XOP-NEXT: retq
|
||||
%x = load <4 x i32>, <4 x i32> *%px, align 16
|
||||
%y = load <4 x i32>, <4 x i32> *%py, align 16
|
||||
%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
|
||||
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
|
||||
%mx = and <4 x i32> %mask, <i32 42, i32 42, i32 42, i32 42>
|
||||
%my = and <4 x i32> %notmask, %y
|
||||
%r = or <4 x i32> %mx, %my
|
||||
ret <4 x i32> %r
|
||||
}
|
||||
|
||||
define <4 x i32> @in_constant_42_vary(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
|
||||
; CHECK-SSE1-LABEL: in_constant_42_vary:
|
||||
; CHECK-SSE1: # %bb.0:
|
||||
; CHECK-SSE1-NEXT: movaps (%rdx), %xmm0
|
||||
; CHECK-SSE1-NEXT: movaps {{.*#+}} xmm1 = [5.885454e-44,5.885454e-44,5.885454e-44,5.885454e-44]
|
||||
; CHECK-SSE1-NEXT: xorps %xmm0, %xmm1
|
||||
; CHECK-SSE1-NEXT: andps (%rcx), %xmm1
|
||||
; CHECK-SSE1-NEXT: xorps %xmm0, %xmm1
|
||||
; CHECK-SSE1-NEXT: movaps %xmm1, (%rdi)
|
||||
; CHECK-SSE1-NEXT: movq %rdi, %rax
|
||||
; CHECK-SSE1-NEXT: retq
|
||||
;
|
||||
; CHECK-SSE2-LABEL: in_constant_42_vary:
|
||||
; CHECK-SSE2: # %bb.0:
|
||||
; CHECK-SSE2-NEXT: movaps (%rsi), %xmm1
|
||||
; CHECK-SSE2-NEXT: movaps {{.*#+}} xmm0 = [42,42,42,42]
|
||||
; CHECK-SSE2-NEXT: xorps %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: andps (%rdx), %xmm0
|
||||
; CHECK-SSE2-NEXT: xorps %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: retq
|
||||
;
|
||||
; CHECK-XOP-LABEL: in_constant_42_vary:
|
||||
; CHECK-XOP: # %bb.0:
|
||||
; CHECK-XOP-NEXT: vmovaps (%rsi), %xmm0
|
||||
; CHECK-XOP-NEXT: vxorps {{.*}}(%rip), %xmm0, %xmm1
|
||||
; CHECK-XOP-NEXT: vandps (%rdx), %xmm1, %xmm1
|
||||
; CHECK-XOP-NEXT: vxorps %xmm0, %xmm1, %xmm0
|
||||
; CHECK-XOP-NEXT: retq
|
||||
%x = load <4 x i32>, <4 x i32> *%px, align 16
|
||||
%y = load <4 x i32>, <4 x i32> *%py, align 16
|
||||
%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
|
||||
%n0 = xor <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %y ; %x
|
||||
%n1 = and <4 x i32> %n0, %mask
|
||||
%r = xor <4 x i32> %n1, %y
|
||||
ret <4 x i32> %r
|
||||
}
|
||||
|
||||
; This is not a canonical form. Testing for completeness only.
|
||||
define <4 x i32> @out_constant_42_vary_invmask(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
|
||||
; CHECK-SSE1-LABEL: out_constant_42_vary_invmask:
|
||||
; CHECK-SSE1: # %bb.0:
|
||||
; CHECK-SSE1-NEXT: movaps (%rcx), %xmm0
|
||||
; CHECK-SSE1-NEXT: movaps %xmm0, %xmm1
|
||||
; CHECK-SSE1-NEXT: andnps {{.*}}(%rip), %xmm1
|
||||
; CHECK-SSE1-NEXT: andps (%rdx), %xmm0
|
||||
; CHECK-SSE1-NEXT: orps %xmm1, %xmm0
|
||||
; CHECK-SSE1-NEXT: movaps %xmm0, (%rdi)
|
||||
; CHECK-SSE1-NEXT: movq %rdi, %rax
|
||||
; CHECK-SSE1-NEXT: retq
|
||||
;
|
||||
; CHECK-SSE2-LABEL: out_constant_42_vary_invmask:
|
||||
; CHECK-SSE2: # %bb.0:
|
||||
; CHECK-SSE2-NEXT: movaps (%rdx), %xmm0
|
||||
; CHECK-SSE2-NEXT: movaps %xmm0, %xmm1
|
||||
; CHECK-SSE2-NEXT: andnps {{.*}}(%rip), %xmm1
|
||||
; CHECK-SSE2-NEXT: andps (%rsi), %xmm0
|
||||
; CHECK-SSE2-NEXT: orps %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: retq
|
||||
;
|
||||
; CHECK-XOP-LABEL: out_constant_42_vary_invmask:
|
||||
; CHECK-XOP: # %bb.0:
|
||||
; CHECK-XOP-NEXT: vmovdqa (%rsi), %xmm0
|
||||
; CHECK-XOP-NEXT: vmovdqa (%rdx), %xmm1
|
||||
; CHECK-XOP-NEXT: vpcmov %xmm1, {{.*}}(%rip), %xmm0, %xmm0
|
||||
; CHECK-XOP-NEXT: retq
|
||||
%x = load <4 x i32>, <4 x i32> *%px, align 16
|
||||
%y = load <4 x i32>, <4 x i32> *%py, align 16
|
||||
%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
|
||||
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
|
||||
%mx = and <4 x i32> %notmask, <i32 42, i32 42, i32 42, i32 42>
|
||||
%my = and <4 x i32> %mask, %y
|
||||
%r = or <4 x i32> %mx, %my
|
||||
ret <4 x i32> %r
|
||||
}
|
||||
|
||||
; This is not a canonical form. Testing for completeness only.
|
||||
define <4 x i32> @in_constant_42_vary_invmask(<4 x i32> *%px, <4 x i32> *%py, <4 x i32> *%pmask) {
|
||||
; CHECK-SSE1-LABEL: in_constant_42_vary_invmask:
|
||||
; CHECK-SSE1: # %bb.0:
|
||||
; CHECK-SSE1-NEXT: movaps (%rdx), %xmm0
|
||||
; CHECK-SSE1-NEXT: movaps (%rcx), %xmm1
|
||||
; CHECK-SSE1-NEXT: movaps {{.*#+}} xmm2 = [5.885454e-44,5.885454e-44,5.885454e-44,5.885454e-44]
|
||||
; CHECK-SSE1-NEXT: xorps %xmm0, %xmm2
|
||||
; CHECK-SSE1-NEXT: andnps %xmm2, %xmm1
|
||||
; CHECK-SSE1-NEXT: xorps %xmm0, %xmm1
|
||||
; CHECK-SSE1-NEXT: movaps %xmm1, (%rdi)
|
||||
; CHECK-SSE1-NEXT: movq %rdi, %rax
|
||||
; CHECK-SSE1-NEXT: retq
|
||||
;
|
||||
; CHECK-SSE2-LABEL: in_constant_42_vary_invmask:
|
||||
; CHECK-SSE2: # %bb.0:
|
||||
; CHECK-SSE2-NEXT: movaps (%rsi), %xmm1
|
||||
; CHECK-SSE2-NEXT: movaps (%rdx), %xmm0
|
||||
; CHECK-SSE2-NEXT: movaps {{.*#+}} xmm2 = [42,42,42,42]
|
||||
; CHECK-SSE2-NEXT: xorps %xmm1, %xmm2
|
||||
; CHECK-SSE2-NEXT: andnps %xmm2, %xmm0
|
||||
; CHECK-SSE2-NEXT: xorps %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: retq
|
||||
;
|
||||
; CHECK-XOP-LABEL: in_constant_42_vary_invmask:
|
||||
; CHECK-XOP: # %bb.0:
|
||||
; CHECK-XOP-NEXT: vmovaps (%rsi), %xmm0
|
||||
; CHECK-XOP-NEXT: vmovaps (%rdx), %xmm1
|
||||
; CHECK-XOP-NEXT: vxorps {{.*}}(%rip), %xmm0, %xmm2
|
||||
; CHECK-XOP-NEXT: vandnps %xmm2, %xmm1, %xmm1
|
||||
; CHECK-XOP-NEXT: vxorps %xmm0, %xmm1, %xmm0
|
||||
; CHECK-XOP-NEXT: retq
|
||||
%x = load <4 x i32>, <4 x i32> *%px, align 16
|
||||
%y = load <4 x i32>, <4 x i32> *%py, align 16
|
||||
%mask = load <4 x i32>, <4 x i32> *%pmask, align 16
|
||||
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
|
||||
%n0 = xor <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %y ; %x
|
||||
%n1 = and <4 x i32> %n0, %notmask
|
||||
%r = xor <4 x i32> %n1, %y
|
||||
ret <4 x i32> %r
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
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Reference in New Issue