Clean up code after renaming LowerSubregs -> ExpandPostRAPseudos.

No functional change intended.

llvm-svn: 140470

llvm/include/llvm/CodeGen/Passes.h

@@ -132,11 +132,10 @@ namespace llvm {
   ///
   FunctionPass *createPrologEpilogCodeInserter();
 
-  /// LowerSubregs Pass - This pass lowers subregs to register-register copies
+  /// ExpandPostRAPseudos Pass - This pass expands pseudo instructions after
-  /// which yields suboptimal, but correct code if the register allocator
+  /// register allocation.
-  /// cannot coalesce all subreg operations during allocation.
   ///
-  FunctionPass *createLowerSubregsPass();
+  FunctionPass *createExpandPostRAPseudosPass();
 
   /// createPostRAScheduler - This pass performs post register allocation
   /// scheduling.

llvm/lib/CodeGen/ExpandPostRAPseudos.cpp

@@ -1,4 +1,4 @@
-//===-- LowerSubregs.cpp - Subregister Lowering instruction pass ----------===//
+//===-- ExpandPostRAPseudos.cpp - Pseudo instruction expansion pass -------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -7,14 +7,12 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file defines a MachineFunction pass which runs after register
+// This file defines a pass that expands COPY and SUBREG_TO_REG pseudo
-// allocation that turns subreg insert/extract instructions into register
+// instructions after register allocation.
-// copies, as needed. This ensures correct codegen even if the coalescer
-// isn't able to remove all subreg instructions.
 //
 //===----------------------------------------------------------------------===//
 
-#define DEBUG_TYPE "lowersubregs"
+#define DEBUG_TYPE "postrapseudos"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/Function.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
@@ -29,52 +27,51 @@
 using namespace llvm;
 
 namespace {
-  struct LowerSubregsInstructionPass : public MachineFunctionPass {
+struct ExpandPostRA : public MachineFunctionPass {
-  private:
+private:
-    const TargetRegisterInfo *TRI;
+  const TargetRegisterInfo *TRI;
-    const TargetInstrInfo *TII;
+  const TargetInstrInfo *TII;
 
-  public:
+public:
-    static char ID; // Pass identification, replacement for typeid
+  static char ID; // Pass identification, replacement for typeid
-    LowerSubregsInstructionPass() : MachineFunctionPass(ID) {}
+  ExpandPostRA() : MachineFunctionPass(ID) {}
 
-    const char *getPassName() const {
+  const char *getPassName() const {
-      return "Subregister lowering instruction pass";
+    return "Post-RA pseudo instruction expansion pass";
-    }
+  }
 
-    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+  virtual void getAnalysisUsage(AnalysisUsage &AU) const {
-      AU.setPreservesCFG();
+    AU.setPreservesCFG();
-      AU.addPreservedID(MachineLoopInfoID);
+    AU.addPreservedID(MachineLoopInfoID);
-      AU.addPreservedID(MachineDominatorsID);
+    AU.addPreservedID(MachineDominatorsID);
-      MachineFunctionPass::getAnalysisUsage(AU);
+    MachineFunctionPass::getAnalysisUsage(AU);
-    }
+  }
 
-    /// runOnMachineFunction - pass entry point
+  /// runOnMachineFunction - pass entry point
-    bool runOnMachineFunction(MachineFunction&);
+  bool runOnMachineFunction(MachineFunction&);
 
-  private:
+private:
-    bool LowerSubregToReg(MachineInstr *MI);
+  bool LowerSubregToReg(MachineInstr *MI);
-    bool LowerCopy(MachineInstr *MI);
+  bool LowerCopy(MachineInstr *MI);
 
-    void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
+  void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
-                          const TargetRegisterInfo *TRI);
+                        const TargetRegisterInfo *TRI);
-    void TransferImplicitDefs(MachineInstr *MI);
+  void TransferImplicitDefs(MachineInstr *MI);
-  };
+};
+} // end anonymous namespace
 
-  char LowerSubregsInstructionPass::ID = 0;
+char ExpandPostRA::ID = 0;
-}
 
-FunctionPass *llvm::createLowerSubregsPass() {
+FunctionPass *llvm::createExpandPostRAPseudosPass() {
-  return new LowerSubregsInstructionPass();
+  return new ExpandPostRA();
 }
 
 /// TransferDeadFlag - MI is a pseudo-instruction with DstReg dead,
 /// and the lowered replacement instructions immediately precede it.
 /// Mark the replacement instructions with the dead flag.
 void
-LowerSubregsInstructionPass::TransferDeadFlag(MachineInstr *MI,
+ExpandPostRA::TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
-                                              unsigned DstReg,
+                               const TargetRegisterInfo *TRI) {
-                                              const TargetRegisterInfo *TRI) {
   for (MachineBasicBlock::iterator MII =
         prior(MachineBasicBlock::iterator(MI)); ; --MII) {
     if (MII->addRegisterDead(DstReg, TRI))
@@ -88,7 +85,7 @@ LowerSubregsInstructionPass::TransferDeadFlag(MachineInstr *MI,
 /// replacement instructions immediately precede it.  Copy any implicit-def
 /// operands from MI to the replacement instruction.
 void
-LowerSubregsInstructionPass::TransferImplicitDefs(MachineInstr *MI) {
+ExpandPostRA::TransferImplicitDefs(MachineInstr *MI) {
   MachineBasicBlock::iterator CopyMI = MI;
   --CopyMI;
 
@@ -100,7 +97,7 @@ LowerSubregsInstructionPass::TransferImplicitDefs(MachineInstr *MI) {
   }
 }
 
-bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
+bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
   MachineBasicBlock *MBB = MI->getParent();
   assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
          MI->getOperand(1).isImm() &&
@@ -152,7 +149,7 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
   return true;
 }
 
-bool LowerSubregsInstructionPass::LowerCopy(MachineInstr *MI) {
+bool ExpandPostRA::LowerCopy(MachineInstr *MI) {
   MachineOperand &DstMO = MI->getOperand(0);
   MachineOperand &SrcMO = MI->getOperand(1);
 
@@ -191,9 +188,9 @@ bool LowerSubregsInstructionPass::LowerCopy(MachineInstr *MI) {
 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
 /// copies.
 ///
-bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
+bool ExpandPostRA::runOnMachineFunction(MachineFunction &MF) {
   DEBUG(dbgs() << "Machine Function\n"
-               << "********** LOWERING SUBREG INSTRS **********\n"
+               << "********** EXPANDING POST-RA PSEUDO INSTRS **********\n"
                << "********** Function: "
                << MF.getFunction()->getName() << '\n');
   TRI = MF.getTarget().getRegisterInfo();

llvm/lib/CodeGen/LLVMTargetMachine.cpp

@@ -444,8 +444,8 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
   if (addPostRegAlloc(PM, OptLevel))
     printAndVerify(PM, "After PostRegAlloc passes");
 
-  PM.add(createLowerSubregsPass());
+  PM.add(createExpandPostRAPseudosPass());
-  printAndVerify(PM, "After LowerSubregs");
+  printAndVerify(PM, "After ExpandPostRAPseudos");
 
   // Insert prolog/epilog code.  Eliminate abstract frame index references...
   PM.add(createPrologEpilogCodeInserter());

llvm/lib/Target/PTX/PTXTargetMachine.cpp

@@ -323,8 +323,8 @@ bool PTXTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
   if (addPostRegAlloc(PM, OptLevel))
     printAndVerify(PM, "After PostRegAlloc passes");
 
-  PM.add(createLowerSubregsPass());
+  PM.add(createExpandPostRAPseudosPass());
-  printAndVerify(PM, "After LowerSubregs");
+  printAndVerify(PM, "After ExpandPostRAPseudos");
 
   // Insert prolog/epilog code.  Eliminate abstract frame index references...
   PM.add(createPrologEpilogCodeInserter());