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[AArch64][SVE] Add reg+imm addressing mode for unpredicated stores 

Reviewers: sdesmalen, efriedma, david-arm

Reviewed By: efriedma

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, danielkiss, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82985
This commit is contained in:
Kerry McLaughlin 2020-07-02 10:41:49 +01:00
parent 421c02e5c6
commit fd6193d5ea
2 changed files with 110 additions and 2 deletions
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10
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
View File

@ -1693,8 +1693,14 @@ multiclass sve_prefetch<SDPatternOperator prefetch, ValueType PredTy, Instructio
multiclass unpred_store<PatFrag Store, ValueType Ty, Instruction RegImmInst,
Instruction PTrue> {
def : Pat<(Store (Ty ZPR:$val), (am_sve_fi GPR64sp:$base, simm4s1:$offset)),
(RegImmInst ZPR:$val, (PTrue 31), GPR64sp:$base, simm4s1:$offset)>;
let AddedComplexity = 1 in {
def _imm : Pat<(Store (Ty ZPR:$val), (am_sve_indexed_s4 GPR64sp:$base, simm4s1:$offset)),
(RegImmInst ZPR:$val, (PTrue 31), GPR64sp:$base, simm4s1:$offset)>;
}
let AddedComplexity = 2 in {
def _fi : Pat<(Store (Ty ZPR:$val), (am_sve_fi GPR64sp:$base, simm4s1:$offset)),
(RegImmInst ZPR:$val, (PTrue 31), GPR64sp:$base, simm4s1:$offset)>;
}
def : Pat<(Store (Ty ZPR:$val), GPR64:$base),
(RegImmInst ZPR:$val, (PTrue 31), GPR64:$base, (i64 0))>;

102
llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll Normal file
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@ -0,0 +1,102 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
; ST1B
define void @st1b_lower_bound(<vscale x 16 x i8> %data, <vscale x 16 x i8>* %a) {
; CHECK-LABEL: st1b_lower_bound:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: st1b { z0.b }, p0, [x0, #-8, mul vl]
; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %a, i64 -8
store <vscale x 16 x i8> %data, <vscale x 16 x i8>* %base
ret void
}
define void @st1b_inbound(<vscale x 16 x i8> %data, <vscale x 16 x i8>* %a) {
; CHECK-LABEL: st1b_inbound:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: st1b { z0.b }, p0, [x0, #1, mul vl]
; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %a, i64 1
store <vscale x 16 x i8> %data, <vscale x 16 x i8>* %base
ret void
}
define void @st1b_upper_bound(<vscale x 16 x i8> %data, <vscale x 16 x i8>* %a) {
; CHECK-LABEL: st1b_upper_bound:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: st1b { z0.b }, p0, [x0, #7, mul vl]
; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %a, i64 7
store <vscale x 16 x i8> %data, <vscale x 16 x i8>* %base
ret void
}
define void @st1b_out_of_upper_bound(<vscale x 16 x i8> %data, <vscale x 16 x i8>* %a) {
; CHECK-LABEL: st1b_out_of_upper_bound:
; CHECK: // %bb.0:
; CHECK-NEXT: rdvl x8, #8
; CHECK-NEXT: add x8, x0, x8
; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: st1b { z0.b }, p0, [x8]
; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %a, i64 8
store <vscale x 16 x i8> %data, <vscale x 16 x i8>* %base
ret void
}
define void @st1b_out_of_lower_bound(<vscale x 16 x i8> %data, <vscale x 16 x i8>* %a) {
; CHECK-LABEL: st1b_out_of_lower_bound:
; CHECK: // %bb.0:
; CHECK-NEXT: rdvl x8, #-9
; CHECK-NEXT: add x8, x0, x8
; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: st1b { z0.b }, p0, [x8]
; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %a, i64 -9
store <vscale x 16 x i8> %data, <vscale x 16 x i8>* %base
ret void
}
; ST1H
define void @st1h_inbound(<vscale x 8 x i16> %data, <vscale x 8 x i16>* %a) {
; CHECK-LABEL: st1h_inbound:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: st1h { z0.h }, p0, [x0, #-6, mul vl]
; CHECK-NEXT: ret
%base = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %a, i64 -6
store <vscale x 8 x i16> %data, <vscale x 8 x i16>* %base
ret void
}
; ST1W
define void @st1w_inbound(<vscale x 4 x i32> %data, <vscale x 4 x i32>* %a) {
; CHECK-LABEL: st1w_inbound:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: st1w { z0.s }, p0, [x0, #2, mul vl]
; CHECK-NEXT: ret
%base = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %a, i64 2
store <vscale x 4 x i32> %data, <vscale x 4 x i32>* %base
ret void
}
; ST1D
define void @st1d_inbound(<vscale x 2 x i64> %data, <vscale x 2 x i64>* %a) {
; CHECK-LABEL: st1d_inbound:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: st1d { z0.d }, p0, [x0, #5, mul vl]
; CHECK-NEXT: ret
%base = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %a, i64 5
store <vscale x 2 x i64> %data, <vscale x 2 x i64>* %base
ret void
}