forked from OSchip/llvm-project
Eliminate the need for ExpandOp to set 'needsanotheriteration', as it already
relegalizes the stuff it returns. Add the ability to custom expand ADD/SUB, so that targets don't need to deal with ADD_PARTS/SUB_PARTS if they don't want. Fix some obscure potential bugs and simplify code. llvm-svn: 25732
This commit is contained in:
Chris Lattner
parent
10f677508f
commit
fd4a7f76a9
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@ -143,9 +143,6 @@ private:
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SDOperand &Lo, SDOperand &Hi);
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void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
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SDOperand &Lo, SDOperand &Hi);
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void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
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SDOperand &Lo, SDOperand &Hi);
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void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain);
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SDOperand getIntPtrConstant(uint64_t Val) {
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@ -3335,26 +3332,6 @@ SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
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return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0));
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}
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/// ExpandAddSub - Find a clever way to expand this add operation into
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/// subcomponents.
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void SelectionDAGLegalize::
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ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
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SDOperand &Lo, SDOperand &Hi) {
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// Expand the subcomponents.
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SDOperand LHSL, LHSH, RHSL, RHSH;
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ExpandOp(LHS, LHSL, LHSH);
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ExpandOp(RHS, RHSL, RHSH);
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std::vector<SDOperand> Ops;
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Ops.push_back(LHSL);
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Ops.push_back(LHSH);
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Ops.push_back(RHSL);
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Ops.push_back(RHSH);
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std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
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Lo = DAG.getNode(NodeOp, VTs, Ops);
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Hi = Lo.getValue(1);
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}
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void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
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SDOperand Op, SDOperand Amt,
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SDOperand &Lo, SDOperand &Hi) {
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@ -3841,11 +3818,6 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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return;
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}
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// Expanding to multiple registers needs to perform an optimization step, and
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// is not careful to avoid operations the target does not support. Make sure
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// that all generated operations are legalized in the next iteration.
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NeedsAnotherIteration = true;
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switch (Node->getOpcode()) {
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case ISD::CopyFromReg:
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assert(0 && "CopyFromReg must be legal!");
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@ -3887,11 +3859,9 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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}
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case ISD::BUILD_PAIR:
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// Legalize both operands. FIXME: in the future we should handle the case
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// where the two elements are not legal.
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assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!");
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Lo = LegalizeOp(Node->getOperand(0));
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Hi = LegalizeOp(Node->getOperand(1));
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// Return the operands.
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Lo = Node->getOperand(0);
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Hi = Node->getOperand(1);
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break;
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case ISD::SIGN_EXTEND_INREG:
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@ -3951,12 +3921,13 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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}
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case ISD::VAARG: {
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SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
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SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
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SDOperand Ch = Node->getOperand(0); // Legalize the chain.
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SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
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Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
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Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
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// Remember that we legalized the chain.
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Hi = LegalizeOp(Hi);
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AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
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if (!TLI.isLittleEndian())
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std::swap(Lo, Hi);
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@ -3964,16 +3935,15 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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}
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case ISD::LOAD: {
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SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
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SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
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SDOperand Ch = Node->getOperand(0); // Legalize the chain.
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SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
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Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
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// Increment the pointer to the other half.
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unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
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Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
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getIntPtrConstant(IncrementSize));
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//Is this safe? declaring that the two parts of the split load
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//are from the same instruction?
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// FIXME: This creates a bogus srcvalue!
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Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
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// Build a factor node to remember that this load is independent of the
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@ -3982,14 +3952,14 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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Hi.getValue(1));
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// Remember that we legalized the chain.
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AddLegalizedOperand(Op.getValue(1), TF);
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AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
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if (!TLI.isLittleEndian())
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std::swap(Lo, Hi);
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break;
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}
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case ISD::VLOAD: {
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SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
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SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
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SDOperand Ch = Node->getOperand(0); // Legalize the chain.
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SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
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unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue();
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MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
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@ -4002,8 +3972,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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unsigned IncrementSize = MVT::getSizeInBits(EVT)/8;
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Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
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getIntPtrConstant(IncrementSize));
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//Is this safe? declaring that the two parts of the split load
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//are from the same instruction?
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// FIXME: This creates a bogus srcvalue!
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Hi = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4));
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} else {
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NumElements /= 2; // Split the vector in half
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@ -4011,8 +3980,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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unsigned IncrementSize = NumElements * MVT::getSizeInBits(EVT)/8;
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Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
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getIntPtrConstant(IncrementSize));
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//Is this safe? declaring that the two parts of the split load
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//are from the same instruction?
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// FIXME: This creates a bogus srcvalue!
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Hi = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4));
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}
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@ -4022,7 +3990,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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Hi.getValue(1));
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// Remember that we legalized the chain.
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AddLegalizedOperand(Op.getValue(1), TF);
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AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
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if (!TLI.isLittleEndian())
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std::swap(Lo, Hi);
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break;
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@ -4088,13 +4056,11 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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Node->getOperand(1), TL, FL, Node->getOperand(4));
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Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
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Node->getOperand(1), TH, FH, Node->getOperand(4));
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Lo = LegalizeOp(Lo);
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Hi = LegalizeOp(Hi);
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break;
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}
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case ISD::SEXTLOAD: {
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SDOperand Chain = LegalizeOp(Node->getOperand(0));
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SDOperand Ptr = LegalizeOp(Node->getOperand(1));
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SDOperand Chain = Node->getOperand(0);
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SDOperand Ptr = Node->getOperand(1);
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MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
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if (EVT == NVT)
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@ -4104,20 +4070,18 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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EVT);
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// Remember that we legalized the chain.
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AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
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AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
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// The high part is obtained by SRA'ing all but one of the bits of the lo
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// part.
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unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
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Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
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TLI.getShiftAmountTy()));
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Lo = LegalizeOp(Lo);
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Hi = LegalizeOp(Hi);
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break;
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}
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case ISD::ZEXTLOAD: {
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SDOperand Chain = LegalizeOp(Node->getOperand(0));
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SDOperand Ptr = LegalizeOp(Node->getOperand(1));
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SDOperand Chain = Node->getOperand(0);
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SDOperand Ptr = Node->getOperand(1);
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MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
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if (EVT == NVT)
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@ -4127,16 +4091,15 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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EVT);
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// Remember that we legalized the chain.
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AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
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AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
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// The high part is just a zero.
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Hi = LegalizeOp(DAG.getConstant(0, NVT));
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Lo = LegalizeOp(Lo);
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Hi = DAG.getConstant(0, NVT);
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break;
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}
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case ISD::EXTLOAD: {
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SDOperand Chain = LegalizeOp(Node->getOperand(0));
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SDOperand Ptr = LegalizeOp(Node->getOperand(1));
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SDOperand Chain = Node->getOperand(0);
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SDOperand Ptr = Node->getOperand(1);
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MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
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if (EVT == NVT)
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@ -4146,73 +4109,38 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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EVT);
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// Remember that we legalized the chain.
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AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
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AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
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// The high part is undefined.
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Hi = LegalizeOp(DAG.getNode(ISD::UNDEF, NVT));
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Lo = LegalizeOp(Lo);
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break;
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}
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case ISD::ANY_EXTEND: {
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SDOperand In;
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switch (getTypeAction(Node->getOperand(0).getValueType())) {
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case Expand: assert(0 && "expand-expand not implemented yet!");
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case Legal: In = LegalizeOp(Node->getOperand(0)); break;
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case Promote:
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In = PromoteOp(Node->getOperand(0));
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break;
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}
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// The low part is any extension of the input (which degenerates to a copy).
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Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, In);
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// The high part is undefined.
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Hi = DAG.getNode(ISD::UNDEF, NVT);
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break;
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}
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case ISD::ANY_EXTEND:
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// The low part is any extension of the input (which degenerates to a copy).
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Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
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// The high part is undefined.
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Hi = DAG.getNode(ISD::UNDEF, NVT);
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break;
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case ISD::SIGN_EXTEND: {
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SDOperand In;
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switch (getTypeAction(Node->getOperand(0).getValueType())) {
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case Expand: assert(0 && "expand-expand not implemented yet!");
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case Legal: In = LegalizeOp(Node->getOperand(0)); break;
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case Promote:
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In = PromoteOp(Node->getOperand(0));
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// Emit the appropriate sign_extend_inreg to get the value we want.
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In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In,
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DAG.getValueType(Node->getOperand(0).getValueType()));
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break;
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}
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// The low part is just a sign extension of the input (which degenerates to
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// a copy).
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Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In);
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Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
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// The high part is obtained by SRA'ing all but one of the bits of the lo
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// part.
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unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
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Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
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TLI.getShiftAmountTy()));
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Hi = DAG.getNode(ISD::SRA, NVT, Lo,
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DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
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break;
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}
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case ISD::ZERO_EXTEND: {
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SDOperand In;
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switch (getTypeAction(Node->getOperand(0).getValueType())) {
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case Expand: assert(0 && "expand-expand not implemented yet!");
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case Legal: In = LegalizeOp(Node->getOperand(0)); break;
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case Promote:
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In = PromoteOp(Node->getOperand(0));
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// Emit the appropriate zero_extend_inreg to get the value we want.
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In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType());
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break;
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}
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case ISD::ZERO_EXTEND:
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// The low part is just a zero extension of the input (which degenerates to
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// a copy).
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Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In);
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Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
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// The high part is just a zero.
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Hi = DAG.getConstant(0, NVT);
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break;
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}
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case ISD::BIT_CONVERT: {
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SDOperand Tmp = ExpandBIT_CONVERT(Node->getValueType(0),
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@ -4221,18 +4149,16 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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break;
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}
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case ISD::READCYCLECOUNTER: {
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case ISD::READCYCLECOUNTER:
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assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
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TargetLowering::Custom &&
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"Must custom expand ReadCycleCounter");
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SDOperand T = TLI.LowerOperation(Op, DAG);
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assert(T.Val && "Node must be custom expanded!");
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Lo = LegalizeOp(T.getValue(0));
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Hi = LegalizeOp(T.getValue(1));
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Lo = TLI.LowerOperation(Op, DAG);
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assert(Lo.Val && "Node must be custom expanded!");
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Hi = Lo.getValue(1);
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AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
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LegalizeOp(T.getValue(2)));
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LegalizeOp(Lo.getValue(2)));
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break;
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}
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// These operators cannot be expanded directly, emit them as calls to
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// library functions.
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@ -4241,8 +4167,8 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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SDOperand Op;
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switch (getTypeAction(Node->getOperand(0).getValueType())) {
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case Expand: assert(0 && "cannot expand FP!");
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case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
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case Promote: Op = PromoteOp(Node->getOperand(0)); break;
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case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
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case Promote: Op = PromoteOp (Node->getOperand(0)); break;
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}
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Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
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@ -4263,11 +4189,16 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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case ISD::FP_TO_UINT:
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if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
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SDOperand Op = DAG.getNode(ISD::FP_TO_UINT, VT,
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LegalizeOp(Node->getOperand(0)));
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// Now that the custom expander is done, expand the result, which is still
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// VT.
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Op = TLI.LowerOperation(Op, DAG);
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SDOperand Op;
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switch (getTypeAction(Node->getOperand(0).getValueType())) {
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case Expand: assert(0 && "cannot expand FP!");
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case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
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case Promote: Op = PromoteOp (Node->getOperand(0)); break;
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}
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Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
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// Now that the custom expander is done, expand the result.
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if (Op.Val) {
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ExpandOp(Op, Lo, Hi);
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break;
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@ -4284,8 +4215,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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// If the target wants custom lowering, do so.
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SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
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if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
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SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0),
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ShiftAmt);
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SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
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Op = TLI.LowerOperation(Op, DAG);
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if (Op.Val) {
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// Now that the custom expander is done, expand the result, which is
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@ -4317,8 +4247,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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// If the target wants custom lowering, do so.
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SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
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if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
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SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0),
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ShiftAmt);
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SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
|
||||
Op = TLI.LowerOperation(Op, DAG);
|
||||
if (Op.Val) {
|
||||
// Now that the custom expander is done, expand the result, which is
|
||||
|
|
@ -4350,8 +4279,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
|
|||
// If the target wants custom lowering, do so.
|
||||
SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
|
||||
if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
|
||||
SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0),
|
||||
ShiftAmt);
|
||||
SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
|
||||
Op = TLI.LowerOperation(Op, DAG);
|
||||
if (Op.Val) {
|
||||
// Now that the custom expander is done, expand the result, which is
|
||||
|
|
@ -4380,13 +4308,34 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
|
|||
}
|
||||
|
||||
case ISD::ADD:
|
||||
ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1),
|
||||
Lo, Hi);
|
||||
break;
|
||||
case ISD::SUB:
|
||||
ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1),
|
||||
Lo, Hi);
|
||||
case ISD::SUB: {
|
||||
// If the target wants to custom expand this, let them.
|
||||
if (TLI.getOperationAction(Node->getOpcode(), VT) ==
|
||||
TargetLowering::Custom) {
|
||||
Op = TLI.LowerOperation(Op, DAG);
|
||||
if (Op.Val) {
|
||||
ExpandOp(Op, Lo, Hi);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// Expand the subcomponents.
|
||||
SDOperand LHSL, LHSH, RHSL, RHSH;
|
||||
ExpandOp(Node->getOperand(0), LHSL, LHSH);
|
||||
ExpandOp(Node->getOperand(1), RHSL, RHSH);
|
||||
|
||||
std::vector<SDOperand> Ops;
|
||||
Ops.push_back(LHSL);
|
||||
Ops.push_back(LHSH);
|
||||
Ops.push_back(RHSL);
|
||||
Ops.push_back(RHSH);
|
||||
std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
|
||||
unsigned Opc =
|
||||
Node->getOpcode() == ISD::ADD ? ISD::ADD_PARTS : ISD::SUB_PARTS;
|
||||
Lo = DAG.getNode(Opc, VTs, Ops);
|
||||
Hi = Lo.getValue(1);
|
||||
break;
|
||||
}
|
||||
case ISD::MUL: {
|
||||
if (TLI.isOperationLegal(ISD::MULHU, NVT)) {
|
||||
SDOperand LL, LH, RL, RH;
|
||||
|
|
|
|||
Loading…
Reference in New Issue