forked from OSchip/llvm-project
AMDGPU: Start adding offset fields to flat instructions
llvm-svn: 305194
This commit is contained in:
Matt Arsenault
parent
14d61436c0
commit
fd02314113
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@ -138,7 +138,8 @@ private:
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bool SelectMUBUFIntrinsicVOffset(SDValue Offset, SDValue &SOffset,
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SDValue &ImmOffset, SDValue &VOffset) const;
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bool SelectFlat(SDValue Addr, SDValue &VAddr, SDValue &SLC) const;
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bool SelectFlat(SDValue Addr, SDValue &VAddr,
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SDValue &Offset, SDValue &SLC) const;
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bool SelectSMRDOffset(SDValue ByteOffsetNode, SDValue &Offset,
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bool &Imm) const;
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@ -1315,8 +1316,10 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFIntrinsicVOffset(SDValue Offset,
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bool AMDGPUDAGToDAGISel::SelectFlat(SDValue Addr,
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SDValue &VAddr,
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SDValue &Offset,
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SDValue &SLC) const {
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VAddr = Addr;
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Offset = CurDAG->getTargetConstant(0, SDLoc(), MVT::i16);
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SLC = CurDAG->getTargetConstant(0, SDLoc(), MVT::i1);
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return true;
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}
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@ -126,8 +126,9 @@ bool AMDGPUInstructionSelector::selectG_STORE(MachineInstr &I) const {
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MachineInstr *Flat = BuildMI(*BB, &I, DL, TII.get(AMDGPU::FLAT_STORE_DWORD))
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.add(I.getOperand(1))
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.add(I.getOperand(0))
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.addImm(0)
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.addImm(0);
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.addImm(0) // offset
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.addImm(0) // glc
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.addImm(0); // slc
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// Now that we selected an opcode, we need to constrain the register
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@ -392,8 +393,9 @@ bool AMDGPUInstructionSelector::selectG_LOAD(MachineInstr &I) const {
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MachineInstr *Flat = BuildMI(*BB, &I, DL, TII.get(Opcode))
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.add(I.getOperand(0))
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.addReg(PtrReg)
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.addImm(0)
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.addImm(0);
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.addImm(0) // offset
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.addImm(0) // glc
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.addImm(0); // slc
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bool Ret = constrainSelectedInstRegOperands(*Flat, TII, TRI, RBI);
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I.eraseFromParent();
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@ -285,6 +285,9 @@ public:
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bool isOffset() const { return isImmTy(ImmTyOffset) && isUInt<16>(getImm()); }
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bool isOffset0() const { return isImmTy(ImmTyOffset0) && isUInt<16>(getImm()); }
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bool isOffset1() const { return isImmTy(ImmTyOffset1) && isUInt<8>(getImm()); }
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bool isOffsetU12() const { return isImmTy(ImmTyOffset) && isUInt<12>(getImm()); }
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bool isOffsetS13() const { return isImmTy(ImmTyOffset) && isInt<13>(getImm()); }
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bool isGDS() const { return isImmTy(ImmTyGDS); }
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bool isGLC() const { return isImmTy(ImmTyGLC); }
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bool isSLC() const { return isImmTy(ImmTySLC); }
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@ -886,6 +889,10 @@ public:
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return getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm];
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}
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bool hasFlatOffsets() const {
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return getFeatureBits()[AMDGPU::FeatureFlatInstOffsets];
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}
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bool hasSGPR102_SGPR103() const {
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return !isVI();
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}
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@ -1034,6 +1041,8 @@ public:
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AMDGPUOperand::Ptr defaultSMRDOffset8() const;
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AMDGPUOperand::Ptr defaultSMRDOffset20() const;
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AMDGPUOperand::Ptr defaultSMRDLiteralOffset() const;
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AMDGPUOperand::Ptr defaultOffsetU12() const;
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AMDGPUOperand::Ptr defaultOffsetS13() const;
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OperandMatchResultTy parseOModOperand(OperandVector &Operands);
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@ -1970,6 +1979,15 @@ unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
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}
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}
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if ((TSFlags & SIInstrFlags::FLAT) && !hasFlatOffsets()) {
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// FIXME: Produces error without correct column reported.
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auto OpNum =
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AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::offset);
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const auto &Op = Inst.getOperand(OpNum);
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if (Op.getImm() != 0)
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return Match_InvalidOperand;
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}
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return Match_Success;
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}
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@ -3849,6 +3867,14 @@ AMDGPUOperand::Ptr AMDGPUAsmParser::defaultSMRDLiteralOffset() const {
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return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyOffset);
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}
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AMDGPUOperand::Ptr AMDGPUAsmParser::defaultOffsetU12() const {
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return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyOffset);
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}
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AMDGPUOperand::Ptr AMDGPUAsmParser::defaultOffsetS13() const {
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return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyOffset);
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}
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//===----------------------------------------------------------------------===//
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// vop3
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//===----------------------------------------------------------------------===//
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@ -7,7 +7,7 @@
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//
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//===----------------------------------------------------------------------===//
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def FLATAtomic : ComplexPattern<i64, 2, "SelectFlat">;
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def FLATAtomic : ComplexPattern<i64, 3, "SelectFlat">;
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//===----------------------------------------------------------------------===//
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// FLAT classes
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@ -55,6 +55,8 @@ class FLAT_Real <bits<7> op, FLAT_Pseudo ps> :
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// copy relevant pseudo op flags
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let SubtargetPredicate = ps.SubtargetPredicate;
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let AsmMatchConverter = ps.AsmMatchConverter;
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let TSFlags = ps.TSFlags;
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let UseNamedOperandTable = ps.UseNamedOperandTable;
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// encoding fields
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bits<8> vaddr;
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@ -63,10 +65,23 @@ class FLAT_Real <bits<7> op, FLAT_Pseudo ps> :
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bits<1> slc;
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bits<1> glc;
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// Only valid on gfx9
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bits<1> lds = 0; // XXX - What does this actually do?
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bits<2> seg; // Segment, 00=flat, 01=scratch, 10=global, 11=reserved
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// Signed offset. Highest bit ignored for flat and treated as 12-bit
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// unsigned for flat acceses.
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bits<13> offset;
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bits<1> nv = 0; // XXX - What does this actually do?
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// We don't use tfe right now, and it was removed in gfx9.
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bits<1> tfe = 0;
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// 15-0 is reserved.
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// Only valid on GFX9+
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let Inst{12-0} = offset;
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let Inst{13} = lds;
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let Inst{15-14} = 0;
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let Inst{16} = !if(ps.has_glc, glc, ps.glcValue);
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let Inst{17} = slc;
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let Inst{24-18} = op;
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@ -74,24 +89,30 @@ class FLAT_Real <bits<7> op, FLAT_Pseudo ps> :
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let Inst{39-32} = vaddr;
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let Inst{47-40} = !if(ps.has_data, vdata, ?);
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// 54-48 is reserved.
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let Inst{55} = tfe;
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let Inst{55} = nv; // nv on GFX9+, TFE before.
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let Inst{63-56} = !if(ps.has_vdst, vdst, ?);
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}
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class FLAT_Load_Pseudo <string opName, RegisterClass regClass> : FLAT_Pseudo<
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class FLAT_Load_Pseudo <string opName, RegisterClass regClass,
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bit HasSignedOffset = 0> : FLAT_Pseudo<
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opName,
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(outs regClass:$vdst),
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(ins VReg_64:$vaddr, GLC:$glc, slc:$slc),
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" $vdst, $vaddr$glc$slc"> {
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!if(HasSignedOffset,
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(ins VReg_64:$vaddr, offset_s13:$offset, GLC:$glc, slc:$slc),
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(ins VReg_64:$vaddr, offset_u12:$offset, GLC:$glc, slc:$slc)),
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" $vdst, $vaddr$offset$glc$slc"> {
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let has_data = 0;
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let mayLoad = 1;
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}
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class FLAT_Store_Pseudo <string opName, RegisterClass vdataClass> : FLAT_Pseudo<
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class FLAT_Store_Pseudo <string opName, RegisterClass vdataClass,
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bit HasSignedOffset = 0> : FLAT_Pseudo<
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opName,
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(outs),
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(ins VReg_64:$vaddr, vdataClass:$vdata, GLC:$glc, slc:$slc),
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" $vaddr, $vdata$glc$slc"> {
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!if(HasSignedOffset,
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(ins VReg_64:$vaddr, vdataClass:$vdata, offset_s13:$offset, GLC:$glc, slc:$slc),
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(ins VReg_64:$vaddr, vdataClass:$vdata, offset_u12:$offset, GLC:$glc, slc:$slc)),
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" $vaddr, $vdata$offset$glc$slc"> {
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let mayLoad = 0;
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let mayStore = 1;
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let has_vdst = 0;
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@ -103,12 +124,15 @@ multiclass FLAT_Atomic_Pseudo<
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ValueType vt,
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SDPatternOperator atomic = null_frag,
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ValueType data_vt = vt,
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RegisterClass data_rc = vdst_rc> {
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RegisterClass data_rc = vdst_rc,
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bit HasSignedOffset = 0> {
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def "" : FLAT_Pseudo <opName,
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(outs),
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(ins VReg_64:$vaddr, data_rc:$vdata, slc:$slc),
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" $vaddr, $vdata$slc",
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!if(HasSignedOffset,
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(ins VReg_64:$vaddr, data_rc:$vdata, offset_s13:$offset, slc:$slc),
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(ins VReg_64:$vaddr, data_rc:$vdata, offset_u12:$offset, slc:$slc)),
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" $vaddr, $vdata$offset$slc",
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[]>,
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AtomicNoRet <NAME, 0> {
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let mayLoad = 1;
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@ -121,10 +145,12 @@ multiclass FLAT_Atomic_Pseudo<
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def _RTN : FLAT_Pseudo <opName,
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(outs vdst_rc:$vdst),
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(ins VReg_64:$vaddr, data_rc:$vdata, slc:$slc),
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" $vdst, $vaddr, $vdata glc$slc",
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!if(HasSignedOffset,
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(ins VReg_64:$vaddr, data_rc:$vdata, offset_s13:$offset, slc:$slc),
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(ins VReg_64:$vaddr, data_rc:$vdata, offset_u12:$offset, slc:$slc)),
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" $vdst, $vaddr, $vdata$offset glc$slc",
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[(set vt:$vdst,
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(atomic (FLATAtomic i64:$vaddr, i1:$slc), data_vt:$vdata))]>,
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(atomic (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$vdata))]>,
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AtomicNoRet <NAME, 1> {
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let mayLoad = 1;
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let mayStore = 1;
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@ -313,30 +339,30 @@ def flat_truncstorei16 : flat_st <truncstorei16>;
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// Patterns for global loads with no offset.
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class FlatLoadPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : Pat <
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(vt (node i64:$addr)),
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(inst $addr, 0, 0)
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(inst $addr, 0, 0, 0)
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>;
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class FlatLoadAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : Pat <
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(vt (node i64:$addr)),
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(inst $addr, 1, 0)
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(inst $addr, 0, 1, 0)
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>;
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class FlatStorePat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : Pat <
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(node vt:$data, i64:$addr),
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(inst $addr, $data, 0, 0)
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(inst $addr, $data, 0, 0, 0)
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>;
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class FlatStoreAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : Pat <
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// atomic store follows atomic binop convention so the address comes
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// first.
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(node i64:$addr, vt:$data),
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(inst $addr, $data, 1, 0)
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(inst $addr, $data, 0, 1, 0)
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>;
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class FlatAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt,
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ValueType data_vt = vt> : Pat <
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(vt (node i64:$addr, data_vt:$data)),
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(inst $addr, $data, 0)
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(inst $addr, $data, 0, 0)
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>;
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let Predicates = [isCIVI] in {
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@ -492,11 +492,21 @@ class NamedOperandU8<string Name, AsmOperandClass MatchClass> : Operand<i8> {
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let ParserMatchClass = MatchClass;
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}
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class NamedOperandU12<string Name, AsmOperandClass MatchClass> : Operand<i16> {
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let PrintMethod = "print"#Name;
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let ParserMatchClass = MatchClass;
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}
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class NamedOperandU16<string Name, AsmOperandClass MatchClass> : Operand<i16> {
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let PrintMethod = "print"#Name;
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let ParserMatchClass = MatchClass;
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}
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class NamedOperandS13<string Name, AsmOperandClass MatchClass> : Operand<i16> {
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let PrintMethod = "print"#Name;
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let ParserMatchClass = MatchClass;
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}
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class NamedOperandU32<string Name, AsmOperandClass MatchClass> : Operand<i32> {
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let PrintMethod = "print"#Name;
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let ParserMatchClass = MatchClass;
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@ -514,6 +524,8 @@ def offen : NamedOperandBit<"Offen", NamedMatchClass<"Offen">>;
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def idxen : NamedOperandBit<"Idxen", NamedMatchClass<"Idxen">>;
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def addr64 : NamedOperandBit<"Addr64", NamedMatchClass<"Addr64">>;
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def offset_u12 : NamedOperandU12<"Offset", NamedMatchClass<"OffsetU12">>;
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def offset_s13 : NamedOperandS13<"Offset", NamedMatchClass<"OffsetS13">>;
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def offset : NamedOperandU16<"Offset", NamedMatchClass<"Offset">>;
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def offset0 : NamedOperandU8<"Offset0", NamedMatchClass<"Offset0">>;
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def offset1 : NamedOperandU8<"Offset1", NamedMatchClass<"Offset1">>;
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@ -14,7 +14,7 @@ regBankSelected: true
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# GCN: global_addrspace
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# GCN: [[PTR:%[0-9]+]] = COPY %vgpr0_vgpr1
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# GCN: FLAT_LOAD_DWORD [[PTR]], 0, 0
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# GCN: FLAT_LOAD_DWORD [[PTR]], 0, 0, 0
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body: |
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bb.0:
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@ -15,7 +15,7 @@ regBankSelected: true
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# GCN: global_addrspace
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# GCN: [[PTR:%[0-9]+]] = COPY %vgpr0_vgpr1
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# GCN: [[VAL:%[0-9]+]] = COPY %vgpr2
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# GCN: FLAT_STORE_DWORD [[PTR]], [[VAL]], 0, 0
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# GCN: FLAT_STORE_DWORD [[PTR]], [[VAL]], 0, 0, 0
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body: |
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bb.0:
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@ -219,19 +219,19 @@ body: |
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%34 = V_MOV_B32_e32 63, implicit %exec
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%27 = V_AND_B32_e64 %26, %24, implicit %exec
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FLAT_STORE_DWORD %37, %27, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
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FLAT_STORE_DWORD %37, %27, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
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%28 = V_AND_B32_e64 %24, %26, implicit %exec
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FLAT_STORE_DWORD %37, %28, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
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FLAT_STORE_DWORD %37, %28, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
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%29 = V_AND_B32_e32 %26, %24, implicit %exec
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FLAT_STORE_DWORD %37, %29, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
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FLAT_STORE_DWORD %37, %29, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
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%30 = V_AND_B32_e64 %26, %26, implicit %exec
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FLAT_STORE_DWORD %37, %30, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
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FLAT_STORE_DWORD %37, %30, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
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%31 = V_AND_B32_e64 %34, %34, implicit %exec
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FLAT_STORE_DWORD %37, %31, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
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FLAT_STORE_DWORD %37, %31, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
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S_ENDPGM
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@ -407,34 +407,34 @@ body: |
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%27 = S_MOV_B32 -4
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%11 = V_LSHLREV_B32_e64 12, %10, implicit %exec
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FLAT_STORE_DWORD %20, %11, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
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FLAT_STORE_DWORD %20, %11, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
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%12 = V_LSHLREV_B32_e64 %7, 12, implicit %exec
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FLAT_STORE_DWORD %20, %12, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
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FLAT_STORE_DWORD %20, %12, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
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%13 = V_LSHL_B32_e64 %7, 12, implicit %exec
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FLAT_STORE_DWORD %20, %13, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
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FLAT_STORE_DWORD %20, %13, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
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%14 = V_LSHL_B32_e64 12, %7, implicit %exec
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FLAT_STORE_DWORD %20, %14, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
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FLAT_STORE_DWORD %20, %14, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
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%15 = V_LSHL_B32_e64 12, %24, implicit %exec
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FLAT_STORE_DWORD %20, %15, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
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FLAT_STORE_DWORD %20, %15, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%22 = V_LSHL_B32_e64 %6, 12, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %22, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
FLAT_STORE_DWORD %20, %22, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%23 = V_LSHL_B32_e64 %6, 32, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %23, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
FLAT_STORE_DWORD %20, %23, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%25 = V_LSHL_B32_e32 %6, %6, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %25, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
FLAT_STORE_DWORD %20, %25, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%26 = V_LSHLREV_B32_e32 11, %24, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %26, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
FLAT_STORE_DWORD %20, %26, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%28 = V_LSHL_B32_e32 %27, %6, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %28, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
FLAT_STORE_DWORD %20, %28, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
S_ENDPGM
|
||||
|
||||
|
|
@ -615,34 +615,34 @@ body: |
|
|||
%35 = V_MOV_B32_e32 2, implicit %exec
|
||||
|
||||
%11 = V_ASHRREV_I32_e64 8, %10, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %11, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
FLAT_STORE_DWORD %20, %11, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%12 = V_ASHRREV_I32_e64 %8, %10, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %12, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
FLAT_STORE_DWORD %20, %12, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%13 = V_ASHR_I32_e64 %7, 3, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %13, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
FLAT_STORE_DWORD %20, %13, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%14 = V_ASHR_I32_e64 7, %32, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %14, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
FLAT_STORE_DWORD %20, %14, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%15 = V_ASHR_I32_e64 %27, %24, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %15, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
FLAT_STORE_DWORD %20, %15, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%22 = V_ASHR_I32_e64 %6, 4, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %22, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
FLAT_STORE_DWORD %20, %22, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%23 = V_ASHR_I32_e64 %6, %33, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %23, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
FLAT_STORE_DWORD %20, %23, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%25 = V_ASHR_I32_e32 %34, %34, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %25, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
FLAT_STORE_DWORD %20, %25, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%26 = V_ASHRREV_I32_e32 11, %10, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %26, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
FLAT_STORE_DWORD %20, %26, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%28 = V_ASHR_I32_e32 %27, %35, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %28, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
FLAT_STORE_DWORD %20, %28, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
S_ENDPGM
|
||||
|
||||
|
|
@ -824,34 +824,34 @@ body: |
|
|||
%35 = V_MOV_B32_e32 2, implicit %exec
|
||||
|
||||
%11 = V_LSHRREV_B32_e64 8, %10, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %11, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
FLAT_STORE_DWORD %20, %11, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%12 = V_LSHRREV_B32_e64 %8, %10, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %12, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
FLAT_STORE_DWORD %20, %12, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%13 = V_LSHR_B32_e64 %7, 3, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %13, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
FLAT_STORE_DWORD %20, %13, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%14 = V_LSHR_B32_e64 7, %32, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %14, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
FLAT_STORE_DWORD %20, %14, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%15 = V_LSHR_B32_e64 %27, %24, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %15, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
FLAT_STORE_DWORD %20, %15, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%22 = V_LSHR_B32_e64 %6, 4, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %22, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
FLAT_STORE_DWORD %20, %22, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%23 = V_LSHR_B32_e64 %6, %33, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %23, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
FLAT_STORE_DWORD %20, %23, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%25 = V_LSHR_B32_e32 %34, %34, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %25, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
FLAT_STORE_DWORD %20, %25, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%26 = V_LSHRREV_B32_e32 11, %10, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %26, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
FLAT_STORE_DWORD %20, %26, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
%28 = V_LSHR_B32_e32 %27, %35, implicit %exec
|
||||
FLAT_STORE_DWORD %20, %28, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
FLAT_STORE_DWORD %20, %28, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
|
||||
|
||||
S_ENDPGM
|
||||
|
||||
|
|
|
|||
|
|
@ -246,15 +246,15 @@ body: |
|
|||
S_BRANCH %bb.1
|
||||
|
||||
bb.1:
|
||||
FLAT_STORE_DWORDX2 %vgpr0_vgpr1, %vgpr2_vgpr3, 0, 0, implicit %exec, implicit %flat_scr
|
||||
FLAT_STORE_DWORDX2 %vgpr0_vgpr1, %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr3 = V_MOV_B32_e32 0, implicit %exec
|
||||
FLAT_STORE_DWORDX3 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4, 0, 0, implicit %exec, implicit %flat_scr
|
||||
FLAT_STORE_DWORDX3 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr3 = V_MOV_B32_e32 0, implicit %exec
|
||||
FLAT_STORE_DWORDX4 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, implicit %exec, implicit %flat_scr
|
||||
FLAT_STORE_DWORDX4 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr3 = V_MOV_B32_e32 0, implicit %exec
|
||||
FLAT_ATOMIC_CMPSWAP_X2 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4_vgpr5, 0, implicit %exec, implicit %flat_scr
|
||||
FLAT_ATOMIC_CMPSWAP_X2 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr3 = V_MOV_B32_e32 0, implicit %exec
|
||||
FLAT_ATOMIC_FCMPSWAP_X2 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4_vgpr5, 0, implicit %exec, implicit %flat_scr
|
||||
FLAT_ATOMIC_FCMPSWAP_X2 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr3 = V_MOV_B32_e32 0, implicit %exec
|
||||
S_ENDPGM
|
||||
|
||||
|
|
|
|||
|
|
@ -57,15 +57,15 @@ body: |
|
|||
%4.sub1 = COPY %3.sub0
|
||||
undef %5.sub0 = COPY %4.sub1
|
||||
%5.sub1 = COPY %4.sub0
|
||||
FLAT_STORE_DWORDX2 %vgpr0_vgpr1, killed %5, 0, 0, implicit %exec, implicit %flat_scr
|
||||
FLAT_STORE_DWORDX2 %vgpr0_vgpr1, killed %5, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
|
||||
%6 = IMPLICIT_DEF
|
||||
undef %7.sub0_sub1 = COPY %6
|
||||
%7.sub2 = COPY %3.sub0
|
||||
FLAT_STORE_DWORDX3 %vgpr0_vgpr1, killed %7, 0, 0, implicit %exec, implicit %flat_scr
|
||||
FLAT_STORE_DWORDX3 %vgpr0_vgpr1, killed %7, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
|
||||
%8 = IMPLICIT_DEF
|
||||
undef %9.sub0_sub1_sub2 = COPY %8
|
||||
%9.sub3 = COPY %3.sub0
|
||||
FLAT_STORE_DWORDX4 %vgpr0_vgpr1, killed %9, 0, 0, implicit %exec, implicit %flat_scr
|
||||
FLAT_STORE_DWORDX4 %vgpr0_vgpr1, killed %9, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
...
|
||||
|
|
|
|||
|
|
@ -58,12 +58,12 @@ body: |
|
|||
|
||||
bb.3:
|
||||
%1 = COPY killed %17
|
||||
FLAT_STORE_DWORD undef %10, %1.sub2, 0, 0, implicit %exec, implicit %flat_scr
|
||||
FLAT_STORE_DWORD undef %10, %1.sub2, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%14 = COPY %1.sub1
|
||||
%16 = COPY killed %1.sub0
|
||||
undef %15.sub0 = COPY killed %16
|
||||
%15.sub1 = COPY killed %14
|
||||
FLAT_STORE_DWORDX2 undef %11, killed %15, 0, 0, implicit %exec, implicit %flat_scr
|
||||
FLAT_STORE_DWORDX2 undef %11, killed %15, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
S_ENDPGM
|
||||
|
||||
...
|
||||
|
|
|
|||
|
|
@ -214,26 +214,26 @@ body: |
|
|||
%15 = S_ADDC_U32 %7.sub1, %0.sub1, implicit-def dead %scc, implicit %scc
|
||||
%16 = REG_SEQUENCE %14, 1, %15, 2
|
||||
%18 = COPY %16
|
||||
%17 = FLAT_LOAD_DWORD %18, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.uglygep45)
|
||||
%17 = FLAT_LOAD_DWORD %18, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.uglygep45)
|
||||
%60 = V_BFE_U32 %17, 8, 8, implicit %exec
|
||||
%61 = V_LSHLREV_B32_e32 2, killed %60, implicit %exec
|
||||
%70 = V_ADD_I32_e32 %7.sub0, %61, implicit-def %vcc, implicit %exec
|
||||
%66 = COPY %13
|
||||
%65 = V_ADDC_U32_e32 0, %66, implicit-def %vcc, implicit %vcc, implicit %exec
|
||||
%67 = REG_SEQUENCE %70, 1, killed %65, 2
|
||||
FLAT_STORE_DWORD %67, %30, 0, 0, implicit %exec, implicit %flat_scr :: (store 4 into %ir.tmp9)
|
||||
FLAT_STORE_DWORD %67, %30, 0, 0, 0, implicit %exec, implicit %flat_scr :: (store 4 into %ir.tmp9)
|
||||
%37 = S_ADD_U32 %14, 4, implicit-def %scc
|
||||
%38 = S_ADDC_U32 %15, 0, implicit-def dead %scc, implicit %scc
|
||||
%71 = COPY killed %37
|
||||
%72 = COPY killed %38
|
||||
%41 = REG_SEQUENCE killed %71, 1, killed %72, 2
|
||||
%40 = FLAT_LOAD_DWORD killed %41, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.scevgep)
|
||||
%40 = FLAT_LOAD_DWORD killed %41, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.scevgep)
|
||||
%73 = V_BFE_U32 %40, 8, 8, implicit %exec
|
||||
%74 = V_LSHLREV_B32_e32 2, killed %73, implicit %exec
|
||||
%83 = V_ADD_I32_e32 %7.sub0, %74, implicit-def %vcc, implicit %exec
|
||||
%78 = V_ADDC_U32_e32 0, %66, implicit-def %vcc, implicit %vcc, implicit %exec
|
||||
%80 = REG_SEQUENCE %83, 1, killed %78, 2
|
||||
FLAT_STORE_DWORD %80, %30, 0, 0, implicit %exec, implicit %flat_scr :: (store 4 into %ir.tmp17)
|
||||
FLAT_STORE_DWORD %80, %30, 0, 0, 0, implicit %exec, implicit %flat_scr :: (store 4 into %ir.tmp17)
|
||||
%55 = S_ADD_U32 %0.sub0, 8, implicit-def %scc
|
||||
%56 = S_ADDC_U32 %0.sub1, 0, implicit-def dead %scc, implicit %scc
|
||||
%57 = REG_SEQUENCE %55, 1, killed %56, 2
|
||||
|
|
@ -377,26 +377,26 @@ body: |
|
|||
%15 = S_ADDC_U32 %7.sub1, %0.sub1, implicit-def dead %scc, implicit %scc
|
||||
%16 = REG_SEQUENCE %14, 1, %15, 2
|
||||
%18 = COPY %16
|
||||
%17 = FLAT_LOAD_DWORD %18, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.uglygep45)
|
||||
%17 = FLAT_LOAD_DWORD %18, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.uglygep45)
|
||||
%60 = V_BFE_U32 %17, 8, 8, implicit %exec
|
||||
%61 = V_LSHLREV_B32_e32 %84, killed %60, implicit %exec
|
||||
%70 = V_ADD_I32_e32 %7.sub0, %61, implicit-def %vcc, implicit %exec
|
||||
%66 = COPY %13
|
||||
%65 = V_ADDC_U32_e32 0, %66, implicit-def %vcc, implicit %vcc, implicit %exec
|
||||
%67 = REG_SEQUENCE %70, 1, killed %65, 2
|
||||
FLAT_STORE_DWORD %67, %30, 0, 0, implicit %exec, implicit %flat_scr :: (store 4 into %ir.tmp9)
|
||||
FLAT_STORE_DWORD %67, %30, 0, 0, 0, implicit %exec, implicit %flat_scr :: (store 4 into %ir.tmp9)
|
||||
%37 = S_ADD_U32 %14, 4, implicit-def %scc
|
||||
%38 = S_ADDC_U32 %15, 0, implicit-def dead %scc, implicit %scc
|
||||
%71 = COPY killed %37
|
||||
%72 = COPY killed %38
|
||||
%41 = REG_SEQUENCE killed %71, 1, killed %72, 2
|
||||
%40 = FLAT_LOAD_DWORD killed %41, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.scevgep)
|
||||
%40 = FLAT_LOAD_DWORD killed %41, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.scevgep)
|
||||
%73 = V_BFE_U32 %40, 8, 8, implicit %exec
|
||||
%74 = V_LSHLREV_B32_e32 %84, killed %73, implicit %exec
|
||||
%83 = V_ADD_I32_e32 %7.sub0, %74, implicit-def %vcc, implicit %exec
|
||||
%78 = V_ADDC_U32_e32 0, %66, implicit-def %vcc, implicit %vcc, implicit %exec
|
||||
%80 = REG_SEQUENCE %83, 1, killed %78, 2
|
||||
FLAT_STORE_DWORD %80, %30, 0, 0, implicit %exec, implicit %flat_scr :: (store 4 into %ir.tmp17)
|
||||
FLAT_STORE_DWORD %80, %30, 0, 0, 0, implicit %exec, implicit %flat_scr :: (store 4 into %ir.tmp17)
|
||||
%55 = S_ADD_U32 %0.sub0, 8, implicit-def %scc
|
||||
%56 = S_ADDC_U32 %0.sub1, 0, implicit-def dead %scc, implicit %scc
|
||||
%57 = REG_SEQUENCE %55, 1, killed %56, 2
|
||||
|
|
|
|||
|
|
@ -51,21 +51,21 @@ name: flat_zero_waitcnt
|
|||
body: |
|
||||
bb.0:
|
||||
successors: %bb.1
|
||||
%vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.global4)
|
||||
%vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 %vgpr7_vgpr8, 0, 0, implicit %exec, implicit %flat_scr :: (load 16 from %ir.global16)
|
||||
%vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.global4)
|
||||
%vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 %vgpr7_vgpr8, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 16 from %ir.global16)
|
||||
%vgpr0 = V_MOV_B32_e32 %vgpr1, implicit %exec
|
||||
S_BRANCH %bb.1
|
||||
|
||||
bb.1:
|
||||
successors: %bb.2
|
||||
%vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 %vgpr7_vgpr8, 0, 0, implicit %exec, implicit %flat_scr :: (load 16 from %ir.global16)
|
||||
%vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 %vgpr7_vgpr8, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 16 from %ir.global16)
|
||||
%vgpr0 = V_MOV_B32_e32 %vgpr1, implicit %exec
|
||||
S_BRANCH %bb.2
|
||||
|
||||
bb.2:
|
||||
%vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.flat4)
|
||||
%vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 %vgpr7_vgpr8, 0, 0, implicit %exec, implicit %flat_scr :: (load 16 from %ir.flat16)
|
||||
%vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.flat4)
|
||||
%vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 %vgpr7_vgpr8, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 16 from %ir.flat16)
|
||||
%vgpr0 = V_MOV_B32_e32 %vgpr1, implicit %exec
|
||||
S_ENDPGM
|
||||
...
|
||||
|
|
@ -86,11 +86,11 @@ name: single_fallthrough_successor_no_end_block_wait
|
|||
body: |
|
||||
bb.0:
|
||||
successors: %bb.1
|
||||
%vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
|
||||
bb.1:
|
||||
%vgpr3_vgpr4 = V_LSHLREV_B64 4, %vgpr7_vgpr8, implicit %exec
|
||||
FLAT_STORE_DWORD %vgpr3_vgpr4, %vgpr0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
FLAT_STORE_DWORD %vgpr3_vgpr4, %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
S_ENDPGM
|
||||
...
|
||||
---
|
||||
|
|
@ -114,15 +114,15 @@ name: single_branch_successor_not_next_block
|
|||
body: |
|
||||
bb.0:
|
||||
successors: %bb.2
|
||||
%vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, implicit %exec, implicit %flat_scr
|
||||
%vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
S_BRANCH %bb.2
|
||||
|
||||
bb.1:
|
||||
FLAT_STORE_DWORD %vgpr8_vgpr9, %vgpr10, 0, 0, implicit %exec, implicit %flat_scr
|
||||
FLAT_STORE_DWORD %vgpr8_vgpr9, %vgpr10, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
S_ENDPGM
|
||||
|
||||
bb.2:
|
||||
%vgpr3_vgpr4 = V_LSHLREV_B64 4, %vgpr7_vgpr8, implicit %exec
|
||||
FLAT_STORE_DWORD %vgpr3_vgpr4, %vgpr0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
FLAT_STORE_DWORD %vgpr3_vgpr4, %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr
|
||||
S_ENDPGM
|
||||
...
|
||||
|
|
|
|||
|
|
@ -0,0 +1,40 @@
|
|||
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN %s
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
|
||||
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding 2>&1 %s | FileCheck -check-prefix=GFX9-ERR -check-prefix=GCNERR %s
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding 2>&1 %s | FileCheck -check-prefix=VI-ERR -check-prefix=GCNERR %s
|
||||
|
||||
|
||||
flat_load_dword v1, v[3:4] offset:0
|
||||
// GCN: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x50,0xdc,0x03,0x00,0x00,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] offset:-1
|
||||
// GCN-ERR: :35: error: failed parsing operand.
|
||||
|
||||
// FIXME: Error on VI in wrong column
|
||||
flat_load_dword v1, v[3:4] offset:4095
|
||||
// GFX9: flat_load_dword v1, v[3:4] offset:4095 ; encoding: [0xff,0x0f,0x50,0xdc,0x03,0x00,0x00,0x01]
|
||||
// VIERR: :1: error: invalid operand for instruction
|
||||
|
||||
flat_load_dword v1, v[3:4] offset:4096
|
||||
// GCNERR: :28: error: invalid operand for instruction
|
||||
|
||||
flat_load_dword v1, v[3:4] offset:4 glc
|
||||
// GFX9: flat_load_dword v1, v[3:4] offset:4 glc ; encoding: [0x04,0x00,0x51,0xdc,0x03,0x00,0x00,0x01]
|
||||
// VIERR: :1: error: invalid operand for instruction
|
||||
|
||||
flat_load_dword v1, v[3:4] offset:4 glc slc
|
||||
// GFX9: flat_load_dword v1, v[3:4] offset:4 glc slc ; encoding: [0x04,0x00,0x53,0xdc,0x03,0x00,0x00,0x01]
|
||||
// VIERR: :1: error: invalid operand for instruction
|
||||
|
||||
flat_atomic_add v[3:4], v5 offset:8 slc
|
||||
// GFX9: flat_atomic_add v[3:4], v5 offset:8 slc ; encoding: [0x08,0x00,0x0a,0xdd,0x03,0x05,0x00,0x00]
|
||||
// VIERR: :1: error: invalid operand for instruction
|
||||
|
||||
flat_atomic_swap v[3:4], v5 offset:16
|
||||
// GFX9: flat_atomic_swap v[3:4], v5 offset:16 ; encoding: [0x10,0x00,0x00,0xdd,0x03,0x05,0x00,0x00]
|
||||
// VIERR: :1: error: invalid operand for instruction
|
||||
|
||||
flat_store_dword v[3:4], v1 offset:16
|
||||
// GFX9: flat_store_dword v[3:4], v1 offset:16 ; encoding: [0x10,0x00,0x70,0xdc,0x03,0x01,0x00,0x00]
|
||||
// VIERR: :1: error: invalid operand for instruction
|
||||
|
|
@ -49,9 +49,10 @@ flat_store_dword v[3:4], v1 slc
|
|||
|
||||
// FIXME: For atomic instructions, glc must be placed immediately following
|
||||
// the data regiser. These forms aren't currently supported:
|
||||
// FIXME: offset:0 required
|
||||
// flat_atomic_add v1, v[3:4], v5 slc glc
|
||||
|
||||
flat_atomic_add v1 v[3:4], v5 glc slc
|
||||
flat_atomic_add v1, v[3:4], v5 offset:0 glc slc
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_add v1, v[3:4], v5 glc slc ; encoding: [0x00,0x00,0xcb,0xdc,0x03,0x05,0x00,0x01]
|
||||
// VI: flat_atomic_add v1, v[3:4], v5 glc slc ; encoding: [0x00,0x00,0x0b,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
|
|
|||
Loading…
Reference in New Issue