From fcf5254fa792353852a6a7604206dd4e93ad0f99 Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Mon, 6 Jan 2020 13:37:29 +0000 Subject: [PATCH] [AMDGPU] Handle frame index base operands in memOpsHaveSameBasePtr Summary: This is in preparation for getMemOperandsWithOffset returning more base operands. Reviewers: arsenm, rampitec Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, arphaman, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D73454 --- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 5 ----- 1 file changed, 5 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index f18f06754a55..d13cb8bec206 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -408,11 +408,6 @@ static bool memOpsHaveSameBasePtr(const MachineInstr &MI1, const MachineOperand &BaseOp1, const MachineInstr &MI2, const MachineOperand &BaseOp2) { - // Support only base operands with base registers. - // Note: this could be extended to support FI operands. - if (!BaseOp1.isReg() || !BaseOp2.isReg()) - return false; - if (BaseOp1.isIdenticalTo(BaseOp2)) return true;