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[X86] Add FPCW as an implicit use on floating point load instructions. 

These instructions can generate a stack overflow exception so technically they read the stack overflow exception mask bit.

llvm-svn: 353564
This commit is contained in:
Craig Topper 2019-02-08 20:50:09 +00:00
parent 784929d045
commit fcb63c4c6c
4 changed files with 10 additions and 10 deletions
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14
llvm/lib/Target/X86/X86InstrFPStack.td
View File

@ -417,7 +417,7 @@ def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RSTi:$op),
} // SchedRW
// Floating point loads & stores.
let SchedRW = [WriteLoad] in {
let SchedRW = [WriteLoad], Uses = [FPCW] in {
let canFoldAsLoad = 1 in {
def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP,
[(set RFP32:$dst, (loadf32 addr:$src))]>;
@ -489,7 +489,7 @@ def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>;
} // mayStore
} // SchedRW, Uses = [FPCW]
let mayLoad = 1, SchedRW = [WriteLoad] in {
let mayLoad = 1, SchedRW = [WriteLoad], Uses = [FPCW] in {
def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">;
def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">;
def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">;
@ -539,7 +539,7 @@ def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">
}
// FP Stack manipulation instructions.
let SchedRW = [WriteMove] in {
let SchedRW = [WriteMove], Uses = [FPCW] in {
def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RSTi:$op), "fld\t$op">;
def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RSTi:$op), "fst\t$op">;
def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RSTi:$op), "fstp\t$op">;
@ -547,7 +547,7 @@ def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RSTi:$op), "fxch\t$op">;
}
// Floating point constant loads.
let SchedRW = [WriteZero] in {
let SchedRW = [WriteZero], Uses = [FPCW] in {
def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
[(set RFP32:$dst, fpimm0)]>;
def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
@ -562,13 +562,13 @@ def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
[(set RFP80:$dst, fpimm1)]>;
}
let SchedRW = [WriteFLD0] in
let SchedRW = [WriteFLD0], Uses = [FPCW] in
def LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz">;
let SchedRW = [WriteFLD1] in
let SchedRW = [WriteFLD1], Uses = [FPCW] in
def LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1">;
let SchedRW = [WriteFLDC] in {
let SchedRW = [WriteFLDC], Uses = [FPCW] in {
def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", []>;
def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", []>;
def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", []>;

2
llvm/test/CodeGen/MIR/X86/memory-operands.mir
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@ -357,7 +357,7 @@ body: |
bb.0.entry:
$rsp = frame-setup SUB64ri8 $rsp, 24, implicit-def dead $eflags
CFI_INSTRUCTION def_cfa_offset 32
LD_F80m $rsp, 1, $noreg, 32, $noreg, implicit-def dead $fpsw
LD_F80m $rsp, 1, $noreg, 32, $noreg, implicit-def dead $fpsw, implicit $fpcw
; CHECK: name: stack_psv
; CHECK: ST_FP80m $rsp, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (store 10 into stack, align 16)
ST_FP80m $rsp, 1, _, 0, _, implicit-def dead $fpsw, implicit $fpcw :: (store 10 into stack, align 16)

2
llvm/test/CodeGen/X86/pr34080.ll
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@ -54,10 +54,10 @@ define void @_Z1fe(x86_fp80 %z) local_unnamed_addr #0 {
; SSE2-SCHEDULE-NEXT: movq %rsp, %rbp
; SSE2-SCHEDULE-NEXT: .cfi_def_cfa_register %rbp
; SSE2-SCHEDULE-NEXT: fnstcw -4(%rbp)
; SSE2-SCHEDULE-NEXT: fldt 16(%rbp)
; SSE2-SCHEDULE-NEXT: movzwl -4(%rbp), %eax
; SSE2-SCHEDULE-NEXT: movw $3199, -4(%rbp) ## imm = 0xC7F
; SSE2-SCHEDULE-NEXT: fldcw -4(%rbp)
; SSE2-SCHEDULE-NEXT: fldt 16(%rbp)
; SSE2-SCHEDULE-NEXT: movw %ax, -4(%rbp)
; SSE2-SCHEDULE-NEXT: fistl -8(%rbp)
; SSE2-SCHEDULE-NEXT: fldcw -4(%rbp)

2
llvm/test/CodeGen/X86/pr40529.ll
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@ -5,10 +5,10 @@ define x86_fp80 @rem_pio2l_min(x86_fp80 %z) {
; CHECK-LABEL: rem_pio2l_min:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fnstcw -{{[0-9]+}}(%rsp)
; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
; CHECK-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax
; CHECK-NEXT: movw $3199, -{{[0-9]+}}(%rsp) # imm = 0xC7F
; CHECK-NEXT: fldcw -{{[0-9]+}}(%rsp)
; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
; CHECK-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: fistl -{{[0-9]+}}(%rsp)
; CHECK-NEXT: fldcw -{{[0-9]+}}(%rsp)