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add support for legalizing an icmp where the result is illegal (4xi1) but 

the input is legal (4 x i32)

llvm-svn: 74964
This commit is contained in:
Chris Lattner 2009-07-07 23:03:54 +00:00
parent cbbf747b7b
commit fc74e8241a
2 changed files with 37 additions and 7 deletions
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37
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View File

@ -891,15 +891,38 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) { void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
MVT LoVT, HiVT; MVT LoVT, HiVT;
DebugLoc dl = N->getDebugLoc(); DebugLoc DL = N->getDebugLoc();
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
// Split the input.
MVT InVT = N->getOperand(0).getValueType();
SDValue LL, LH, RL, RH; SDValue LL, LH, RL, RH;
GetSplitVector(N->getOperand(0), LL, LH); switch (getTypeAction(InVT)) {
GetSplitVector(N->getOperand(1), RL, RH); default: assert(0 && "Unexpected type action!");
case WidenVector: assert(0 && "Unimp");
Lo = DAG.getNode(N->getOpcode(), dl, LoVT, LL, RL, N->getOperand(2)); case Legal: {
Hi = DAG.getNode(N->getOpcode(), dl, HiVT, LH, RH, N->getOperand(2)); assert(LoVT == HiVT && "Legal non-power-of-two vector type?");
MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
LoVT.getVectorNumElements());
LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
DAG.getIntPtrConstant(0));
LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
DAG.getIntPtrConstant(0));
RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
break;
}
case SplitVector:
GetSplitVector(N->getOperand(0), LL, LH);
GetSplitVector(N->getOperand(1), RL, RH);
break;
}
Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

7
llvm/test/CodeGen/X86/vec_compare.ll
View File

@ -5,3 +5,10 @@ define <4 x i32> @test(<4 x i32> %A, <4 x i32> %B) nounwind {
ret <4 x i32> %C ret <4 x i32> %C
} }
define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) nounwind {
%C = icmp sgt <4 x i32> %A, %B
%D = sext <4 x i1> %C to <4 x i32>
ret <4 x i32> %D
}