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[AddDiscriminators] Migrate tests to opaque pointers (NFC) 

Update performed using:
https://gist.github.com/nikic/98357b71fd67756b0f064c9517b62a34

memcpy-discriminator.ll was fixed up to use named instructions
and drop the no longer needed bitcasts.
This commit is contained in:
Nikita Popov 2022-06-22 12:47:12 +02:00
parent 7c802f985f
commit fc655a9edf
11 changed files with 90 additions and 93 deletions
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12
llvm/test/Transforms/AddDiscriminators/basic.ll
View File

@ -15,17 +15,17 @@ define void @foo(i32 %i) #0 !dbg !4 {
entry: entry:
%i.addr = alloca i32, align 4 %i.addr = alloca i32, align 4
%x = alloca i32, align 4 %x = alloca i32, align 4
store i32 %i, i32* %i.addr, align 4 store i32 %i, ptr %i.addr, align 4
%0 = load i32, i32* %i.addr, align 4, !dbg !10 %0 = load i32, ptr %i.addr, align 4, !dbg !10
%cmp = icmp slt i32 %0, 10, !dbg !10 %cmp = icmp slt i32 %0, 10, !dbg !10
br i1 %cmp, label %if.then, label %if.end, !dbg !10 br i1 %cmp, label %if.then, label %if.end, !dbg !10
if.then: ; preds = %entry if.then: ; preds = %entry
%1 = load i32, i32* %i.addr, align 4, !dbg !10 %1 = load i32, ptr %i.addr, align 4, !dbg !10
; CHECK: %1 = load i32, i32* %i.addr, align 4, !dbg ![[THEN:[0-9]+]] ; CHECK: %1 = load i32, ptr %i.addr, align 4, !dbg ![[THEN:[0-9]+]]
store i32 %1, i32* %x, align 4, !dbg !10 store i32 %1, ptr %x, align 4, !dbg !10
; CHECK: store i32 %1, i32* %x, align 4, !dbg ![[THEN]] ; CHECK: store i32 %1, ptr %x, align 4, !dbg ![[THEN]]
br label %if.end, !dbg !10 br label %if.end, !dbg !10
; CHECK: br label %if.end, !dbg ![[THEN]] ; CHECK: br label %if.end, !dbg ![[THEN]]

9
llvm/test/Transforms/AddDiscriminators/call.ll
View File

@ -12,9 +12,8 @@ define void @_Z3foov() #0 !dbg !4 {
call void @_Z3barv(), !dbg !10 call void @_Z3barv(), !dbg !10
; CHECK: call void @_Z3barv(), !dbg ![[CALL0:[0-9]+]] ; CHECK: call void @_Z3barv(), !dbg ![[CALL0:[0-9]+]]
%a = alloca [100 x i8], align 16 %a = alloca [100 x i8], align 16
%b = bitcast [100 x i8]* %a to i8* call void @llvm.lifetime.start.p0(i64 100, ptr %a), !dbg !11
call void @llvm.lifetime.start.p0i8(i64 100, i8* %b), !dbg !11 call void @llvm.lifetime.end.p0(i64 100, ptr %a), !dbg !11
call void @llvm.lifetime.end.p0i8(i64 100, i8* %b), !dbg !11
call void @_Z3barv(), !dbg !11 call void @_Z3barv(), !dbg !11
; CHECK: call void @_Z3barv(), !dbg ![[CALL1:[0-9]+]] ; CHECK: call void @_Z3barv(), !dbg ![[CALL1:[0-9]+]]
call void @_Z3barv(), !dbg !12 call void @_Z3barv(), !dbg !12
@ -23,8 +22,8 @@ define void @_Z3foov() #0 !dbg !4 {
} }
declare void @_Z3barv() #1 declare void @_Z3barv() #1
declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) nounwind argmemonly declare void @llvm.lifetime.start.p0(i64, ptr nocapture) nounwind argmemonly
declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) nounwind argmemonly declare void @llvm.lifetime.end.p0(i64, ptr nocapture) nounwind argmemonly
attributes #0 = { uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #0 = { uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" }

4
llvm/test/Transforms/AddDiscriminators/dbg-declare-discriminator.ll
View File

@ -8,9 +8,9 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata)
; CHECK-LABEL: @test_valid_metadata ; CHECK-LABEL: @test_valid_metadata
define void @test_valid_metadata() { define void @test_valid_metadata() {
%a = alloca i8 %a = alloca i8
call void @llvm.dbg.declare(metadata i8* %a, metadata !2, metadata !5), !dbg !6 call void @llvm.dbg.declare(metadata ptr %a, metadata !2, metadata !5), !dbg !6
%b = alloca i8 %b = alloca i8
call void @llvm.dbg.declare(metadata i8* %b, metadata !9, metadata !5), !dbg !11 call void @llvm.dbg.declare(metadata ptr %b, metadata !9, metadata !5), !dbg !11
ret void ret void
} }

6
llvm/test/Transforms/AddDiscriminators/diamond.ll
View File

@ -14,9 +14,9 @@
; Function Attrs: uwtable ; Function Attrs: uwtable
define void @_Z3fooi(i32 %i) #0 !dbg !4 { define void @_Z3fooi(i32 %i) #0 !dbg !4 {
%1 = alloca i32, align 4 %1 = alloca i32, align 4
store i32 %i, i32* %1, align 4 store i32 %i, ptr %1, align 4
call void @llvm.dbg.declare(metadata i32* %1, metadata !11, metadata !12), !dbg !13 call void @llvm.dbg.declare(metadata ptr %1, metadata !11, metadata !12), !dbg !13
%2 = load i32, i32* %1, align 4, !dbg !14 %2 = load i32, ptr %1, align 4, !dbg !14
%3 = icmp sgt i32 %2, 10, !dbg !16 %3 = icmp sgt i32 %2, 10, !dbg !16
br i1 %3, label %4, label %5, !dbg !17 br i1 %3, label %4, label %5, !dbg !17

16
llvm/test/Transforms/AddDiscriminators/first-only.ll
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@ -18,23 +18,23 @@ entry:
%i.addr = alloca i32, align 4 %i.addr = alloca i32, align 4
%x = alloca i32, align 4 %x = alloca i32, align 4
%y = alloca i32, align 4 %y = alloca i32, align 4
store i32 %i, i32* %i.addr, align 4 store i32 %i, ptr %i.addr, align 4
%0 = load i32, i32* %i.addr, align 4, !dbg !10 %0 = load i32, ptr %i.addr, align 4, !dbg !10
%cmp = icmp slt i32 %0, 10, !dbg !10 %cmp = icmp slt i32 %0, 10, !dbg !10
br i1 %cmp, label %if.then, label %if.end, !dbg !10 br i1 %cmp, label %if.then, label %if.end, !dbg !10
if.then: ; preds = %entry if.then: ; preds = %entry
%1 = load i32, i32* %i.addr, align 4, !dbg !12 %1 = load i32, ptr %i.addr, align 4, !dbg !12
store i32 %1, i32* %x, align 4, !dbg !12 store i32 %1, ptr %x, align 4, !dbg !12
%2 = load i32, i32* %i.addr, align 4, !dbg !14 %2 = load i32, ptr %i.addr, align 4, !dbg !14
; CHECK: %2 = load i32, i32* %i.addr, align 4, !dbg ![[THEN:[0-9]+]] ; CHECK: %2 = load i32, ptr %i.addr, align 4, !dbg ![[THEN:[0-9]+]]
%sub = sub nsw i32 0, %2, !dbg !14 %sub = sub nsw i32 0, %2, !dbg !14
; CHECK: %sub = sub nsw i32 0, %2, !dbg ![[THEN]] ; CHECK: %sub = sub nsw i32 0, %2, !dbg ![[THEN]]
store i32 %sub, i32* %y, align 4, !dbg !14 store i32 %sub, ptr %y, align 4, !dbg !14
; CHECK: store i32 %sub, i32* %y, align 4, !dbg ![[THEN]] ; CHECK: store i32 %sub, ptr %y, align 4, !dbg ![[THEN]]
br label %if.end, !dbg !15 br label %if.end, !dbg !15
; CHECK: br label %if.end, !dbg ![[BR:[0-9]+]] ; CHECK: br label %if.end, !dbg ![[BR:[0-9]+]]

12
llvm/test/Transforms/AddDiscriminators/inlined.ll
View File

@ -13,12 +13,12 @@ target triple = "arm64-apple-ios"
; Function Attrs: noreturn nounwind ssp ; Function Attrs: noreturn nounwind ssp
define i32 @f() local_unnamed_addr #0 !dbg !7 { define i32 @f() local_unnamed_addr #0 !dbg !7 {
entry: entry:
%0 = tail call i64 @llvm.objectsize.i64.p0i8(i8* inttoptr (i64 1 to i8*), i1 false) #2, !dbg !11 %0 = tail call i64 @llvm.objectsize.i64.p0(ptr inttoptr (i64 1 to ptr), i1 false) #2, !dbg !11
br label %for.cond, !dbg !18 br label %for.cond, !dbg !18
for.cond: ; preds = %for.cond, %entry for.cond: ; preds = %for.cond, %entry
; CHECK: %call.i ; CHECK: %call.i
%call.i = tail call i8* @__memset_chk(i8* null, i32 0, i64 0, i64 %0) #2, !dbg !19 %call.i = tail call ptr @__memset_chk(ptr null, i32 0, i64 0, i64 %0) #2, !dbg !19
; CHECK: br label %for.cond, !dbg ![[BR:[0-9]+]] ; CHECK: br label %for.cond, !dbg ![[BR:[0-9]+]]
br label %for.cond, !dbg !20, !llvm.loop !21 br label %for.cond, !dbg !20, !llvm.loop !21
} }
@ -26,16 +26,16 @@ for.cond: ; preds = %for.cond, %entry
; Function Attrs: nounwind ssp ; Function Attrs: nounwind ssp
define i32 @g() local_unnamed_addr #1 !dbg !12 { define i32 @g() local_unnamed_addr #1 !dbg !12 {
entry: entry:
%0 = tail call i64 @llvm.objectsize.i64.p0i8(i8* inttoptr (i64 1 to i8*), i1 false), !dbg !22 %0 = tail call i64 @llvm.objectsize.i64.p0(ptr inttoptr (i64 1 to ptr), i1 false), !dbg !22
%call = tail call i8* @__memset_chk(i8* null, i32 0, i64 0, i64 %0) #2, !dbg !23 %call = tail call ptr @__memset_chk(ptr null, i32 0, i64 0, i64 %0) #2, !dbg !23
ret i32 undef, !dbg !24 ret i32 undef, !dbg !24
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
declare i8* @__memset_chk(i8*, i32, i64, i64) local_unnamed_addr #2 declare ptr @__memset_chk(ptr, i32, i64, i64) local_unnamed_addr #2
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare i64 @llvm.objectsize.i64.p0i8(i8*, i1) #3 declare i64 @llvm.objectsize.i64.p0(ptr, i1) #3
attributes #0 = { noreturn nounwind ssp } attributes #0 = { noreturn nounwind ssp }
attributes #1 = { nounwind ssp } attributes #1 = { nounwind ssp }

54
llvm/test/Transforms/AddDiscriminators/invoke.ll
View File

@ -5,9 +5,9 @@ target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.14.0" target triple = "x86_64-apple-macosx10.14.0"
; Function Attrs: ssp uwtable ; Function Attrs: ssp uwtable
define void @_Z3foov() #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg !8 { define void @_Z3foov() #0 personality ptr @__gxx_personality_v0 !dbg !8 {
entry: entry:
%exn.slot = alloca i8* %exn.slot = alloca ptr
%ehselector.slot = alloca i32 %ehselector.slot = alloca i32
; CHECK: call void @_Z12bar_noexceptv({{.*}} !dbg ![[CALL1:[0-9]+]] ; CHECK: call void @_Z12bar_noexceptv({{.*}} !dbg ![[CALL1:[0-9]+]]
call void @_Z12bar_noexceptv() #4, !dbg !11 call void @_Z12bar_noexceptv() #4, !dbg !11
@ -21,27 +21,27 @@ invoke.cont: ; preds = %entry
br label %try.cont, !dbg !15 br label %try.cont, !dbg !15
lpad: ; preds = %entry lpad: ; preds = %entry
%0 = landingpad { i8*, i32 } %0 = landingpad { ptr, i32 }
catch i8* null, !dbg !16 catch ptr null, !dbg !16
%1 = extractvalue { i8*, i32 } %0, 0, !dbg !16 %1 = extractvalue { ptr, i32 } %0, 0, !dbg !16
store i8* %1, i8** %exn.slot, align 8, !dbg !16 store ptr %1, ptr %exn.slot, align 8, !dbg !16
%2 = extractvalue { i8*, i32 } %0, 1, !dbg !16 %2 = extractvalue { ptr, i32 } %0, 1, !dbg !16
store i32 %2, i32* %ehselector.slot, align 4, !dbg !16 store i32 %2, ptr %ehselector.slot, align 4, !dbg !16
br label %catch, !dbg !16 br label %catch, !dbg !16
catch: ; preds = %lpad catch: ; preds = %lpad
%exn = load i8*, i8** %exn.slot, align 8, !dbg !15 %exn = load ptr, ptr %exn.slot, align 8, !dbg !15
%3 = call i8* @__cxa_begin_catch(i8* %exn) #4, !dbg !15 %3 = call ptr @__cxa_begin_catch(ptr %exn) #4, !dbg !15
invoke void @__cxa_rethrow() #5 invoke void @__cxa_rethrow() #5
to label %unreachable unwind label %lpad1, !dbg !17 to label %unreachable unwind label %lpad1, !dbg !17
lpad1: ; preds = %catch lpad1: ; preds = %catch
%4 = landingpad { i8*, i32 } %4 = landingpad { ptr, i32 }
cleanup, !dbg !19 cleanup, !dbg !19
%5 = extractvalue { i8*, i32 } %4, 0, !dbg !19 %5 = extractvalue { ptr, i32 } %4, 0, !dbg !19
store i8* %5, i8** %exn.slot, align 8, !dbg !19 store ptr %5, ptr %exn.slot, align 8, !dbg !19
%6 = extractvalue { i8*, i32 } %4, 1, !dbg !19 %6 = extractvalue { ptr, i32 } %4, 1, !dbg !19
store i32 %6, i32* %ehselector.slot, align 4, !dbg !19 store i32 %6, ptr %ehselector.slot, align 4, !dbg !19
invoke void @__cxa_end_catch() invoke void @__cxa_end_catch()
to label %invoke.cont2 unwind label %terminate.lpad, !dbg !20 to label %invoke.cont2 unwind label %terminate.lpad, !dbg !20
@ -52,17 +52,17 @@ try.cont: ; preds = %invoke.cont
ret void, !dbg !21 ret void, !dbg !21
eh.resume: ; preds = %invoke.cont2 eh.resume: ; preds = %invoke.cont2
%exn3 = load i8*, i8** %exn.slot, align 8, !dbg !20 %exn3 = load ptr, ptr %exn.slot, align 8, !dbg !20
%sel = load i32, i32* %ehselector.slot, align 4, !dbg !20 %sel = load i32, ptr %ehselector.slot, align 4, !dbg !20
%lpad.val = insertvalue { i8*, i32 } undef, i8* %exn3, 0, !dbg !20 %lpad.val = insertvalue { ptr, i32 } undef, ptr %exn3, 0, !dbg !20
%lpad.val4 = insertvalue { i8*, i32 } %lpad.val, i32 %sel, 1, !dbg !20 %lpad.val4 = insertvalue { ptr, i32 } %lpad.val, i32 %sel, 1, !dbg !20
resume { i8*, i32 } %lpad.val4, !dbg !20 resume { ptr, i32 } %lpad.val4, !dbg !20
terminate.lpad: ; preds = %lpad1 terminate.lpad: ; preds = %lpad1
%7 = landingpad { i8*, i32 } %7 = landingpad { ptr, i32 }
catch i8* null, !dbg !20 catch ptr null, !dbg !20
%8 = extractvalue { i8*, i32 } %7, 0, !dbg !20 %8 = extractvalue { ptr, i32 } %7, 0, !dbg !20
call void @__clang_call_terminate(i8* %8) #6, !dbg !20 call void @__clang_call_terminate(ptr %8) #6, !dbg !20
unreachable, !dbg !20 unreachable, !dbg !20
unreachable: ; preds = %catch unreachable: ; preds = %catch
@ -76,15 +76,15 @@ declare void @_Z3barv() #2
declare i32 @__gxx_personality_v0(...) declare i32 @__gxx_personality_v0(...)
declare i8* @__cxa_begin_catch(i8*) declare ptr @__cxa_begin_catch(ptr)
declare void @__cxa_rethrow() declare void @__cxa_rethrow()
declare void @__cxa_end_catch() declare void @__cxa_end_catch()
; Function Attrs: noinline noreturn nounwind ; Function Attrs: noinline noreturn nounwind
define linkonce_odr hidden void @__clang_call_terminate(i8*) #3 { define linkonce_odr hidden void @__clang_call_terminate(ptr) #3 {
%2 = call i8* @__cxa_begin_catch(i8* %0) #4 %2 = call ptr @__cxa_begin_catch(ptr %0) #4
call void @_ZSt9terminatev() #6 call void @_ZSt9terminatev() #6
unreachable unreachable
} }

16
llvm/test/Transforms/AddDiscriminators/memcpy-discriminator.ll
View File

@ -67,14 +67,12 @@ cond.true:
; CHECK-DAG: ![[SCOPE]] = !DILexicalBlockFile({{.*}}, discriminator: 2) ; CHECK-DAG: ![[SCOPE]] = !DILexicalBlockFile({{.*}}, discriminator: 2)
; CHECK-DAG: ![[BR_LOC]] = !DILocation(line: 16, column: 16, scope: ![[SCOPE]]) ; CHECK-DAG: ![[BR_LOC]] = !DILocation(line: 16, column: 16, scope: ![[SCOPE]])
%0 = bitcast { i64, i32 }* %g_b.coerce to i8*, !dbg !8 call void @llvm.memcpy.p0.p0.i64(ptr align 4 %g_b.coerce, ptr align 4 @g_b, i64 12, i1 false), !dbg !8
%1 = bitcast %struct.B* @g_b to i8*, !dbg !8 %p1 = getelementptr inbounds { i64, i32 }, ptr %g_b.coerce, i32 0, i32 0, !dbg !8
call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %0, i8* align 4 %1, i64 12, i1 false), !dbg !8 %v1 = load i64, ptr %p1, align 4, !dbg !8
%2 = getelementptr inbounds { i64, i32 }, { i64, i32 }* %g_b.coerce, i32 0, i32 0, !dbg !8 %p2 = getelementptr inbounds { i64, i32 }, ptr %g_b.coerce, i32 0, i32 1, !dbg !8
%3 = load i64, i64* %2, align 4, !dbg !8 %v2 = load i32, ptr %p2, align 4, !dbg !8
%4 = getelementptr inbounds { i64, i32 }, { i64, i32 }* %g_b.coerce, i32 0, i32 1, !dbg !8 %call = call i32 @bar(i64 %v1, i32 %v2, i32 33), !dbg !8
%5 = load i32, i32* %4, align 4, !dbg !8
%call = call i32 @bar(i64 %3, i32 %5, i32 33), !dbg !8
br label %cond.end, !dbg !7 br label %cond.end, !dbg !7
cond.end: ; preds = %entry, %cond.true cond.end: ; preds = %entry, %cond.true
@ -84,7 +82,7 @@ cond.end: ; preds = %entry, %cond.true
declare i32 @bar(i64, i32, i32) declare i32 @bar(i64, i32, i32)
declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i1) #1 declare void @llvm.memcpy.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i1) #1
attributes #0 = { noinline nounwind uwtable } attributes #0 = { noinline nounwind uwtable }
attributes #1 = { argmemonly nounwind } attributes #1 = { argmemonly nounwind }

20
llvm/test/Transforms/AddDiscriminators/multiple.ll
View File

@ -14,30 +14,30 @@ define void @foo(i32 %i) #0 !dbg !4 {
entry: entry:
%i.addr = alloca i32, align 4 %i.addr = alloca i32, align 4
%x = alloca i32, align 4 %x = alloca i32, align 4
store i32 %i, i32* %i.addr, align 4 store i32 %i, ptr %i.addr, align 4
%0 = load i32, i32* %i.addr, align 4, !dbg !10 %0 = load i32, ptr %i.addr, align 4, !dbg !10
%cmp = icmp slt i32 %0, 10, !dbg !10 %cmp = icmp slt i32 %0, 10, !dbg !10
br i1 %cmp, label %if.then, label %if.else, !dbg !10 br i1 %cmp, label %if.then, label %if.else, !dbg !10
if.then: ; preds = %entry if.then: ; preds = %entry
%1 = load i32, i32* %i.addr, align 4, !dbg !10 %1 = load i32, ptr %i.addr, align 4, !dbg !10
; CHECK: %1 = load i32, i32* %i.addr, align 4, !dbg ![[THEN:[0-9]+]] ; CHECK: %1 = load i32, ptr %i.addr, align 4, !dbg ![[THEN:[0-9]+]]
store i32 %1, i32* %x, align 4, !dbg !10 store i32 %1, ptr %x, align 4, !dbg !10
; CHECK: store i32 %1, i32* %x, align 4, !dbg ![[THEN]] ; CHECK: store i32 %1, ptr %x, align 4, !dbg ![[THEN]]
br label %if.end, !dbg !10 br label %if.end, !dbg !10
; CHECK: br label %if.end, !dbg ![[THEN]] ; CHECK: br label %if.end, !dbg ![[THEN]]
if.else: ; preds = %entry if.else: ; preds = %entry
%2 = load i32, i32* %i.addr, align 4, !dbg !10 %2 = load i32, ptr %i.addr, align 4, !dbg !10
; CHECK: %2 = load i32, i32* %i.addr, align 4, !dbg ![[ELSE:[0-9]+]] ; CHECK: %2 = load i32, ptr %i.addr, align 4, !dbg ![[ELSE:[0-9]+]]
%sub = sub nsw i32 0, %2, !dbg !10 %sub = sub nsw i32 0, %2, !dbg !10
; CHECK: %sub = sub nsw i32 0, %2, !dbg ![[ELSE]] ; CHECK: %sub = sub nsw i32 0, %2, !dbg ![[ELSE]]
store i32 %sub, i32* %x, align 4, !dbg !10 store i32 %sub, ptr %x, align 4, !dbg !10
; CHECK: store i32 %sub, i32* %x, align 4, !dbg ![[ELSE]] ; CHECK: store i32 %sub, ptr %x, align 4, !dbg ![[ELSE]]
br label %if.end br label %if.end

14
llvm/test/Transforms/AddDiscriminators/no-discriminators.ll
View File

@ -16,25 +16,25 @@ define i32 @foo(i64 %i) #0 !dbg !4 {
entry: entry:
%retval = alloca i32, align 4 %retval = alloca i32, align 4
%i.addr = alloca i64, align 8 %i.addr = alloca i64, align 8
store i64 %i, i64* %i.addr, align 8 store i64 %i, ptr %i.addr, align 8
call void @llvm.dbg.declare(metadata i64* %i.addr, metadata !13, metadata !DIExpression()), !dbg !14 call void @llvm.dbg.declare(metadata ptr %i.addr, metadata !13, metadata !DIExpression()), !dbg !14
%0 = load i64, i64* %i.addr, align 8, !dbg !15 %0 = load i64, ptr %i.addr, align 8, !dbg !15
; CHECK: %0 = load i64, i64* %i.addr, align 8, !dbg ![[ENTRY:[0-9]+]] ; CHECK: %0 = load i64, ptr %i.addr, align 8, !dbg ![[ENTRY:[0-9]+]]
%cmp = icmp slt i64 %0, 5, !dbg !15 %cmp = icmp slt i64 %0, 5, !dbg !15
; CHECK: %cmp = icmp slt i64 %0, 5, !dbg ![[ENTRY:[0-9]+]] ; CHECK: %cmp = icmp slt i64 %0, 5, !dbg ![[ENTRY:[0-9]+]]
br i1 %cmp, label %if.then, label %if.else, !dbg !15 br i1 %cmp, label %if.then, label %if.else, !dbg !15
; CHECK: br i1 %cmp, label %if.then, label %if.else, !dbg ![[ENTRY:[0-9]+]] ; CHECK: br i1 %cmp, label %if.then, label %if.else, !dbg ![[ENTRY:[0-9]+]]
if.then: ; preds = %entry if.then: ; preds = %entry
store i32 2, i32* %retval, !dbg !15 store i32 2, ptr %retval, !dbg !15
br label %return, !dbg !15 br label %return, !dbg !15
if.else: ; preds = %entry if.else: ; preds = %entry
store i32 90, i32* %retval, !dbg !15 store i32 90, ptr %retval, !dbg !15
br label %return, !dbg !15 br label %return, !dbg !15
return: ; preds = %if.else, %if.then return: ; preds = %if.else, %if.then
%1 = load i32, i32* %retval, !dbg !17 %1 = load i32, ptr %retval, !dbg !17
ret i32 %1, !dbg !17 ret i32 %1, !dbg !17
} }

20
llvm/test/Transforms/AddDiscriminators/oneline.ll
View File

@ -13,15 +13,15 @@
define i32 @_Z3fooi(i32 %i) #0 !dbg !4 { define i32 @_Z3fooi(i32 %i) #0 !dbg !4 {
%1 = alloca i32, align 4 %1 = alloca i32, align 4
%2 = alloca i32, align 4 %2 = alloca i32, align 4
store i32 %i, i32* %2, align 4, !tbaa !13 store i32 %i, ptr %2, align 4, !tbaa !13
call void @llvm.dbg.declare(metadata i32* %2, metadata !9, metadata !17), !dbg !18 call void @llvm.dbg.declare(metadata ptr %2, metadata !9, metadata !17), !dbg !18
%3 = load i32, i32* %2, align 4, !dbg !19, !tbaa !13 %3 = load i32, ptr %2, align 4, !dbg !19, !tbaa !13
%4 = icmp eq i32 %3, 3, !dbg !21 %4 = icmp eq i32 %3, 3, !dbg !21
br i1 %4, label %8, label %5, !dbg !22 br i1 %4, label %8, label %5, !dbg !22
; <label>:5 ; preds = %0 ; <label>:5 ; preds = %0
%6 = load i32, i32* %2, align 4, !dbg !23, !tbaa !13 %6 = load i32, ptr %2, align 4, !dbg !23, !tbaa !13
; CHECK: %6 = load i32, i32* %2, align 4, !dbg ![[THEN1:[0-9]+]],{{.*}} ; CHECK: %6 = load i32, ptr %2, align 4, !dbg ![[THEN1:[0-9]+]],{{.*}}
%7 = icmp eq i32 %6, 5, !dbg !24 %7 = icmp eq i32 %6, 5, !dbg !24
; CHECK: %7 = icmp eq i32 %6, 5, !dbg ![[THEN2:[0-9]+]] ; CHECK: %7 = icmp eq i32 %6, 5, !dbg ![[THEN2:[0-9]+]]
@ -30,21 +30,21 @@ define i32 @_Z3fooi(i32 %i) #0 !dbg !4 {
; CHECK: br i1 %7, label %8, label %9, !dbg ![[THEN3:[0-9]+]] ; CHECK: br i1 %7, label %8, label %9, !dbg ![[THEN3:[0-9]+]]
; <label>:8 ; preds = %5, %0 ; <label>:8 ; preds = %5, %0
store i32 100, i32* %1, align 4, !dbg !26 store i32 100, ptr %1, align 4, !dbg !26
; CHECK: store i32 100, i32* %1, align 4, !dbg ![[ELSE:[0-9]+]] ; CHECK: store i32 100, ptr %1, align 4, !dbg ![[ELSE:[0-9]+]]
br label %10, !dbg !26 br label %10, !dbg !26
; CHECK: br label %10, !dbg ![[ELSE]] ; CHECK: br label %10, !dbg ![[ELSE]]
; <label>:9 ; preds = %5 ; <label>:9 ; preds = %5
store i32 99, i32* %1, align 4, !dbg !27 store i32 99, ptr %1, align 4, !dbg !27
; CHECK: store i32 99, i32* %1, align 4, !dbg ![[COMBINE:[0-9]+]] ; CHECK: store i32 99, ptr %1, align 4, !dbg ![[COMBINE:[0-9]+]]
br label %10, !dbg !27 br label %10, !dbg !27
; CHECK: br label %10, !dbg ![[COMBINE]] ; CHECK: br label %10, !dbg ![[COMBINE]]
; <label>:10 ; preds = %9, %8 ; <label>:10 ; preds = %9, %8
%11 = load i32, i32* %1, align 4, !dbg !28 %11 = load i32, ptr %1, align 4, !dbg !28
ret i32 %11, !dbg !28 ret i32 %11, !dbg !28
} }