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[ARM] Remove FeatureNoARM implies ModeThumb. 

Summary:
By removing FeatureNoARM implies ModeThumb, we can detect cases where a
function's target-features contain -thumb-mode (enables ARM codegen for the
function), but the architecture does not support ARM mode. Previously, the
implication caused the FeatureNoARM bit to be cleared for functions with
-thumb-mode, making the assertion in ARMSubtarget::ARMSubtarget [1]
pointless for such functions.

This assertion is the only guard against generating ARM code for
architectures without ARM codegen support. Is there a place where we
could easily generate error messages for the user? At the moment, we
would generate ARM code for Thumb-only architectures. X86 has the same
behavior as ARM, as in it only has an assertion and no error message,
but I think for ARM an error message would be helpful. What do you
think?

For the example below, `llc -mtriple=armv7m-eabi test.ll -o -` will
generate ARM assembler (or fail with an assertion error with this patch).
Note that if we run the resulting assembler through llvm-mc, we get
an appropriate error message, but not when codegen is handled
through clang.

```
define void @bar() #0 {
entry:
  ret void
}

attributes #0 = { "target-features"="-thumb-mode" }
```

[1] c1f7b54cef/lib/Target/ARM/ARMSubtarget.cpp (L147)

Reviewers: t.p.northover, rengolin, peter.smith, aadg, silviu.baranga, richard.barton.arm, echristo

Reviewed By: rengolin, echristo

Subscribers: efriedma, aemerson, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D35569

llvm-svn: 310476
This commit is contained in:
Florian Hahn 2017-08-09 13:53:28 +00:00
parent d9017cc65e
commit fc4b3951e9
2 changed files with 8 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
llvm/lib/Target/ARM/ARM.td
View File

@ -341,9 +341,7 @@ def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
"Enable Thumb2 instructions">;
def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
"Does not support ARM mode execution",
[ModeThumb]>;
"Does not support ARM mode execution">;
//===----------------------------------------------------------------------===//
// ARM ISAa.
@ -504,11 +502,13 @@ def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps,
def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps,
FeatureNoARM,
ModeThumb,
FeatureDB,
FeatureMClass]>;
def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps,
FeatureNoARM,
ModeThumb,
FeatureDB,
FeatureMClass]>;
@ -536,6 +536,7 @@ def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops,
def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops,
FeatureThumb2,
FeatureNoARM,
ModeThumb,
FeatureDB,
FeatureHWDivThumb,
FeatureMClass]>;
@ -543,6 +544,7 @@ def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops,
def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops,
FeatureThumb2,
FeatureNoARM,
ModeThumb,
FeatureDB,
FeatureHWDivThumb,
FeatureMClass,
@ -598,6 +600,7 @@ def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops,
def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",
[HasV8MBaselineOps,
FeatureNoARM,
ModeThumb,
FeatureDB,
FeatureHWDivThumb,
FeatureV7Clrex,
@ -608,6 +611,7 @@ def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",
def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline",
[HasV8MMainlineOps,
FeatureNoARM,
ModeThumb,
FeatureDB,
FeatureHWDivThumb,
Feature8MSecExt,

2
llvm/test/CodeGen/ARM/scavenging.mir
View File

@ -1,4 +1,4 @@
# RUN: llc -o - %s -mtriple=arm-arm-none-eabi -mcpu=cortex-m0 -run-pass scavenger-test | FileCheck %s
# RUN: llc -o - %s -mtriple=thumb-arm-none-eabi -mcpu=cortex-m0 -run-pass scavenger-test | FileCheck %s
---
# CHECK-LABEL: name: scavengebug0
# Make sure we are not spilling/using a physreg used in the very last