Add mayLoad/mayStore markings to ARM 64-bit atomic pseudo-instructions.

llvm-svn: 139179

llvm/lib/Target/ARM/ARMInstrInfo.td

@@ -1611,7 +1611,7 @@ PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
 
 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
 // (These psuedos use a hand-written selection code).
-let usesCustomInserter = 1, Defs = [CPSR] in {
+let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
 def ATOMOR6432   : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
                               (ins GPR:$addr, GPR:$src1, GPR:$src2),
                               NoItinerary, []>;