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[X86] Tag PSLLDQ/PSRLDQ as WriteShuffle scheduler classes instead of shifts. 

Although they are encoded similar to bit shifts, the byte shifts behave like shuffles from a scheduling point of view.

llvm-svn: 331253
This commit is contained in:
Simon Pilgrim 2018-05-01 11:05:42 +00:00
parent d4c58400c5
commit fc0c26f1a6
6 changed files with 25 additions and 39 deletions
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24
llvm/lib/Target/X86/X86InstrAVX512.td
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@ -10044,6 +10044,7 @@ defm VSHUFPD: avx512_shufp<"vshufpd", avx512vl_i64_info, avx512vl_f64_info>, PD,
// AVX-512 - Byte shift Left/Right
//===----------------------------------------------------------------------===//
// FIXME: The SSE/AVX names are PSLLDQri etc. - should we add the i here as well?
multiclass avx512_shift_packed<bits<8> opc, SDNode OpNode, Format MRMr,
Format MRMm, string OpcodeStr,
X86FoldableSchedWrite sched, X86VectorVTInfo _>{
@ -10063,24 +10064,23 @@ multiclass avx512_shift_packed<bits<8> opc, SDNode OpNode, Format MRMr,
multiclass avx512_shift_packed_all<bits<8> opc, SDNode OpNode, Format MRMr,
Format MRMm, string OpcodeStr,
X86FoldableSchedWrite sched, Predicate prd>{
X86SchedWriteWidths sched, Predicate prd>{
let Predicates = [prd] in
defm Z : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
OpcodeStr, sched, v64i8_info>, EVEX_V512;
defm Z : avx512_shift_packed<opc, OpNode, MRMr, MRMm, OpcodeStr,
sched.ZMM, v64i8_info>, EVEX_V512;
let Predicates = [prd, HasVLX] in {
defm Z256 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
OpcodeStr, sched, v32i8x_info>, EVEX_V256;
defm Z128 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
OpcodeStr, sched, v16i8x_info>, EVEX_V128;
defm Z256 : avx512_shift_packed<opc, OpNode, MRMr, MRMm, OpcodeStr,
sched.YMM, v32i8x_info>, EVEX_V256;
defm Z128 : avx512_shift_packed<opc, OpNode, MRMr, MRMm, OpcodeStr,
sched.XMM, v16i8x_info>, EVEX_V128;
}
}
defm VPSLLDQ : avx512_shift_packed_all<0x73, X86vshldq, MRM7r, MRM7m, "vpslldq",
WriteVecShift, HasBWI>, AVX512PDIi8Base,
EVEX_4V, VEX_WIG;
SchedWriteShuffle, HasBWI>,
AVX512PDIi8Base, EVEX_4V, VEX_WIG;
defm VPSRLDQ : avx512_shift_packed_all<0x73, X86vshrdq, MRM3r, MRM3m, "vpsrldq",
WriteVecShift, HasBWI>, AVX512PDIi8Base,
EVEX_4V, VEX_WIG;
SchedWriteShuffle, HasBWI>,
AVX512PDIi8Base, EVEX_4V, VEX_WIG;
multiclass avx512_psadbw_packed<bits<8> opc, SDNode OpNode,
string OpcodeStr, X86FoldableSchedWrite sched,

16
llvm/lib/Target/X86/X86InstrSSE.td
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@ -3446,16 +3446,17 @@ multiclass PDI_binop_ri<bits<8> opc, Format ImmForm, string OpcodeStr,
}
multiclass PDI_binop_ri_all<bits<8> opc, Format ImmForm, string OpcodeStr,
SDNode OpNode, X86FoldableSchedWrite sched> {
SDNode OpNode, X86SchedWriteWidths sched> {
let Predicates = [HasAVX, NoVLX_Or_NoBWI] in
defm V#NAME : PDI_binop_ri<opc, ImmForm, !strconcat("v", OpcodeStr), OpNode,
VR128, v16i8, sched, 0>, VEX_4V, VEX_WIG;
VR128, v16i8, sched.XMM, 0>, VEX_4V, VEX_WIG;
let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in
defm V#NAME#Y : PDI_binop_ri<opc, ImmForm, !strconcat("v", OpcodeStr), OpNode,
VR256, v32i8, sched, 0>,
VR256, v32i8, sched.YMM, 0>,
VEX_4V, VEX_L, VEX_WIG;
let Constraints = "$src1 = $dst" in
defm NAME : PDI_binop_ri<opc, ImmForm, OpcodeStr, OpNode, VR128, v16i8, sched>;
defm NAME : PDI_binop_ri<opc, ImmForm, OpcodeStr, OpNode, VR128, v16i8,
sched.XMM>;
}
let ExeDomain = SSEPackedInt in {
@ -3481,9 +3482,10 @@ let ExeDomain = SSEPackedInt in {
defm PSRAD : PDI_binop_rmi_all<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
v4i32, v8i32, v4i32, WriteVecShift, NoVLX>;
defm PSLLDQ : PDI_binop_ri_all<0x73, MRM7r, "pslldq", X86vshldq, WriteVecShift>;
defm PSRLDQ : PDI_binop_ri_all<0x73, MRM3r, "psrldq", X86vshrdq, WriteVecShift>;
// PSRADQri doesn't exist in SSE[1-3].
defm PSLLDQ : PDI_binop_ri_all<0x73, MRM7r, "pslldq", X86vshldq,
SchedWriteShuffle>;
defm PSRLDQ : PDI_binop_ri_all<0x73, MRM3r, "psrldq", X86vshrdq,
SchedWriteShuffle>;
} // ExeDomain = SSEPackedInt
//===---------------------------------------------------------------------===//

4
llvm/lib/Target/X86/X86SchedBroadwell.td
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@ -386,9 +386,7 @@ def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVD64rr",
"MMX_MOVD64to64rr",
"MMX_MOVQ2DQrr",
"(V?)MOV64toPQIrr",
"(V?)MOVDI2PDIrr",
"(V?)PSLLDQ(Y?)ri",
"(V?)PSRLDQ(Y?)ri")>;
"(V?)MOVDI2PDIrr")>;
def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> {
let Latency = 1;

4
llvm/lib/Target/X86/X86SchedHaswell.td
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@ -723,9 +723,7 @@ def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVD64rr",
"MMX_MOVD64to64rr",
"MMX_MOVQ2DQrr",
"(V?)MOV64toPQIrr",
"(V?)MOVDI2PDIrr",
"(V?)PSLLDQ(Y?)ri",
"(V?)PSRLDQ(Y?)ri")>;
"(V?)MOVDI2PDIrr")>;
def HWWriteResGroup5 : SchedWriteRes<[HWPort6]> {
let Latency = 1;

4
llvm/lib/Target/X86/X86SchedSkylakeClient.td
View File

@ -397,9 +397,7 @@ def: InstRW<[SKLWriteResGroup3], (instregex "COMP_FST0r",
"UCOM_FPr",
"UCOM_Fr",
"(V?)MOV64toPQIrr",
"(V?)MOVDI2PDIrr",
"(V?)PSLLDQ(Y?)ri",
"(V?)PSRLDQ(Y?)ri")>;
"(V?)MOVDI2PDIrr")>;
def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> {
let Latency = 1;

12
llvm/lib/Target/X86/X86SchedSkylakeServer.td
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@ -445,17 +445,7 @@ def: InstRW<[SKXWriteResGroup3], (instregex "COMP_FST0r",
"VMOV64toPQIZrr",
"VMOV64toPQIrr",
"VMOVDI2PDIZrr",
"VMOVDI2PDIrr",
"VPSLLDQYri",
"VPSLLDQZ128rr",
"VPSLLDQZ256rr",
"VPSLLDQZrr",
"(V?)PSLLDQri",
"VPSRLDQYri",
"VPSRLDQZ128rr",
"VPSRLDQZ256rr",
"VPSRLDQZrr",
"(V?)PSRLDQri")>;
"VMOVDI2PDIrr")>;
def SKXWriteResGroup4 : SchedWriteRes<[SKXPort6]> {
let Latency = 1;