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AMDGPU: Fix printed format of SReg_96 

These are artificial, so I think this should only come up with inline
asm comments.

llvm-svn: 358446
This commit is contained in:
Matt Arsenault 2019-04-15 20:42:18 +00:00
parent e0eb13135f
commit fbdd2a1887
2 changed files with 13 additions and 0 deletions
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3
llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
View File

@ -357,6 +357,9 @@ void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O,
} else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(RegNo)) {
O << 'v';
NumRegs = 3;
} else if (MRI.getRegClass(AMDGPU::SReg_96RegClassID).contains(RegNo)) {
O << 's';
NumRegs = 3;
} else if (MRI.getRegClass(AMDGPU::VReg_160RegClassID).contains(RegNo)) {
O << 'v';
NumRegs = 5;

10
llvm/test/CodeGen/AMDGPU/inline-asm.ll
View File

@ -267,3 +267,13 @@ entry:
tail call void asm sideeffect "s_trap ${0:n}", "n"(i32 10) #1
ret void
}
; Make sure tuples of 3 SGPRs are printed with the [] syntax instead
; of the tablegen default.
; CHECK-LABEL: {{^}}sgpr96_name_format:
; CHECK: ; sgpr96 s[0:2]
define amdgpu_kernel void @sgpr96_name_format() {
entry:
tail call void asm sideeffect "; sgpr96 $0", "s"(<3 x i32> <i32 10, i32 11, i32 12>) #1
ret void
}