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Fixed a bug about disassembling AArch64 post-index load/store single element instructions. 

ie. echo "0x00 0x04 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
    echo "0x00 0x00 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
will be disassembled into the same instruction st1 {v0b}[0], [x0], x0.

llvm-svn: 195591
This commit is contained in:
Hao Liu 2013-11-25 01:53:26 +00:00
parent edbeaee857
commit fbd2b4484c
2 changed files with 21 additions and 16 deletions
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23
llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
View File

@ -1117,7 +1117,9 @@ static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn,
bool Is64bitVec = false;
bool IsLoadDup = false;
bool IsLoad = false;
unsigned TransferBytes = 0; // The total number of bytes transferred.
// The total number of bytes transferred.
// TransferBytes = NumVecs * OneLaneBytes
unsigned TransferBytes = 0;
unsigned NumVecs = 0;
unsigned Opc = Inst.getOpcode();
switch (Opc) {
@ -1511,17 +1513,20 @@ static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn,
unsigned Q = fieldFromInstruction(Insn, 30, 1);
unsigned S = fieldFromInstruction(Insn, 10, 3);
unsigned lane = 0;
switch (NumVecs) {
case 1:
lane = (Q << 3) & S;
// Calculate the number of lanes by number of vectors and transfered bytes.
// NumLanes = 16 bytes / bytes of each lane
unsigned NumLanes = 16 / (TransferBytes / NumVecs);
switch (NumLanes) {
case 16: // A vector has 16 lanes, each lane is 1 bytes.
lane = (Q << 3) | S;
break;
case 2:
lane = (Q << 2) & (S >> 1);
break;
case 3:
lane = (Q << 1) & (S >> 2);
case 8:
lane = (Q << 2) | (S >> 1);
break;
case 4:
lane = (Q << 1) | (S >> 2);
break;
case 2:
lane = Q;
break;
}

14
llvm/test/MC/Disassembler/AArch64/neon-instructions.txt
View File

@ -2126,14 +2126,14 @@
# Post-index of vector load/store single N-element structure to/from
# one lane of N consecutive registers (N = 1,2,3,4)
#----------------------------------------------------------------------
# CHECK: ld1 {v0.b}[0], [x0], #1
# CHECK: ld2 {v15.h, v16.h}[0], [x15], #4
# CHECK: ld3 {v31.s, v0.s, v1.s}[0], [sp], x3
# CHECK: ld1 {v0.b}[9], [x0], #1
# CHECK: ld2 {v15.h, v16.h}[7], [x15], #4
# CHECK: ld3 {v31.s, v0.s, v1.s}[3], [sp], x3
# CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #24
# CHECK: st1 {v0.d}[0], [x0], #8
# CHECK: st2 {v31.s, v0.s}[0], [sp], #8
# CHECK: st3 {v15.h, v16.h, v17.h}[0], [x15], #6
# CHECK: st4 {v0.b, v1.b, v2.b, v3.b}[1], [x0], x5
# CHECK: st1 {v0.d}[1], [x0], #8
# CHECK: st2 {v31.s, v0.s}[3], [sp], #8
# CHECK: st3 {v15.h, v16.h, v17.h}[7], [x15], #6
# CHECK: st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5
0x00,0x04,0xdf,0x4d
0xef,0x59,0xff,0x4d
0xff,0xb3,0xc3,0x4d