forked from OSchip/llvm-project
[DAGCombiner] try repeated fdiv divisor transform before building estimate
This was originally part of D61028, but it's an independent diff. If we try the repeated divisor reciprocal transform before producing an estimate sequence, then we have an opportunity to use scalar fdiv. On x86, the trade-off is 1 divss vs. 5 vector FP ops in the default estimate sequence. On recent chips (Skylake, Ryzen), the full-precision division is only 3 cycle throughput, so that's probably the better perf default option and avoids problems from x86's inaccurate estimates. The last 2 tests show that users still have the option to override the defaults by using the function attributes for reciprocal estimates, but those patterns are potentially made faster by converting the vector ops (including ymm ops) to scalar math. Differential Revision: https://reviews.llvm.org/D61149 llvm-svn: 359398
This commit is contained in:
Sanjay Patel
parent
43003f0fec
commit
fb9a5307a9
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@ -11992,6 +11992,9 @@ SDValue DAGCombiner::visitFDIV(SDNode *N) {
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if (SDValue NewSel = foldBinOpIntoSelect(N))
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return NewSel;
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if (SDValue V = combineRepeatedFPDivisors(N))
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return V;
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if (Options.UnsafeFPMath || Flags.hasAllowReciprocal()) {
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// fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable.
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if (N1CFP) {
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@ -12081,9 +12084,6 @@ SDValue DAGCombiner::visitFDIV(SDNode *N) {
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}
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}
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if (SDValue CombineRepeatedDivisors = combineRepeatedFPDivisors(N))
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return CombineRepeatedDivisors;
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return SDValue();
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}
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@ -51,25 +51,17 @@ define <4 x double> @splat_fdiv_v4f64(<4 x double> %x, double %y) {
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define <4 x float> @splat_fdiv_v4f32(<4 x float> %x, float %y) {
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; SSE-LABEL: splat_fdiv_v4f32:
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; SSE: # %bb.0:
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; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
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; SSE-NEXT: rcpps %xmm1, %xmm2
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; SSE-NEXT: mulps %xmm2, %xmm1
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; SSE-NEXT: movaps {{.*#+}} xmm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]
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; SSE-NEXT: subps %xmm1, %xmm3
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; SSE-NEXT: mulps %xmm2, %xmm3
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; SSE-NEXT: addps %xmm2, %xmm3
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; SSE-NEXT: mulps %xmm3, %xmm0
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; SSE-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; SSE-NEXT: divss %xmm1, %xmm2
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; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0,0,0]
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; SSE-NEXT: mulps %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: splat_fdiv_v4f32:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; AVX-NEXT: vdivss %xmm1, %xmm2, %xmm1
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; AVX-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[0,0,0,0]
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; AVX-NEXT: vrcpps %xmm1, %xmm2
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; AVX-NEXT: vmulps %xmm2, %xmm1, %xmm1
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; AVX-NEXT: vmovaps {{.*#+}} xmm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]
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; AVX-NEXT: vsubps %xmm1, %xmm3, %xmm1
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; AVX-NEXT: vmulps %xmm1, %xmm2, %xmm1
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; AVX-NEXT: vaddps %xmm1, %xmm2, %xmm1
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; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%vy = insertelement <4 x float> undef, float %y, i32 0
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@ -90,14 +82,10 @@ define <8 x float> @splat_fdiv_v8f32(<8 x float> %x, float %y) {
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;
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; AVX-LABEL: splat_fdiv_v8f32:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; AVX-NEXT: vdivss %xmm1, %xmm2, %xmm1
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; AVX-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[0,0,0,0]
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; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1
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; AVX-NEXT: vrcpps %ymm1, %ymm2
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; AVX-NEXT: vmulps %ymm2, %ymm1, %ymm1
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; AVX-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
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; AVX-NEXT: vsubps %ymm1, %ymm3, %ymm1
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; AVX-NEXT: vmulps %ymm1, %ymm2, %ymm1
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; AVX-NEXT: vaddps %ymm1, %ymm2, %ymm1
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; AVX-NEXT: vmulps %ymm1, %ymm0, %ymm0
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; AVX-NEXT: retq
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%vy = insertelement <8 x float> undef, float %y, i32 0
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@ -109,25 +97,25 @@ define <8 x float> @splat_fdiv_v8f32(<8 x float> %x, float %y) {
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define <4 x float> @splat_fdiv_v4f32_estimate(<4 x float> %x, float %y) #0 {
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; SSE-LABEL: splat_fdiv_v4f32_estimate:
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; SSE: # %bb.0:
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; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
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; SSE-NEXT: rcpps %xmm1, %xmm2
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; SSE-NEXT: mulps %xmm2, %xmm1
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; SSE-NEXT: movaps {{.*#+}} xmm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]
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; SSE-NEXT: subps %xmm1, %xmm3
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; SSE-NEXT: mulps %xmm2, %xmm3
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; SSE-NEXT: addps %xmm2, %xmm3
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; SSE-NEXT: rcpss %xmm1, %xmm2
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; SSE-NEXT: mulss %xmm2, %xmm1
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; SSE-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
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; SSE-NEXT: subss %xmm1, %xmm3
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; SSE-NEXT: mulss %xmm2, %xmm3
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; SSE-NEXT: addss %xmm2, %xmm3
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; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,0,0,0]
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; SSE-NEXT: mulps %xmm3, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: splat_fdiv_v4f32_estimate:
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; AVX: # %bb.0:
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; AVX-NEXT: vrcpss %xmm1, %xmm1, %xmm2
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; AVX-NEXT: vmulss %xmm2, %xmm1, %xmm1
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; AVX-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero
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; AVX-NEXT: vsubss %xmm1, %xmm3, %xmm1
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; AVX-NEXT: vmulss %xmm1, %xmm2, %xmm1
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; AVX-NEXT: vaddss %xmm1, %xmm2, %xmm1
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; AVX-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[0,0,0,0]
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; AVX-NEXT: vrcpps %xmm1, %xmm2
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; AVX-NEXT: vmulps %xmm2, %xmm1, %xmm1
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; AVX-NEXT: vmovaps {{.*#+}} xmm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]
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; AVX-NEXT: vsubps %xmm1, %xmm3, %xmm1
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; AVX-NEXT: vmulps %xmm1, %xmm2, %xmm1
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; AVX-NEXT: vaddps %xmm1, %xmm2, %xmm1
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; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%vy = insertelement <4 x float> undef, float %y, i32 0
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@ -152,14 +140,14 @@ define <8 x float> @splat_fdiv_v8f32_estimate(<8 x float> %x, float %y) #0 {
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;
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; AVX-LABEL: splat_fdiv_v8f32_estimate:
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; AVX: # %bb.0:
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; AVX-NEXT: vrcpss %xmm1, %xmm1, %xmm2
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; AVX-NEXT: vmulss %xmm2, %xmm1, %xmm1
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; AVX-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero
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; AVX-NEXT: vsubss %xmm1, %xmm3, %xmm1
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; AVX-NEXT: vmulss %xmm1, %xmm2, %xmm1
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; AVX-NEXT: vaddss %xmm1, %xmm2, %xmm1
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; AVX-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[0,0,0,0]
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; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1
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; AVX-NEXT: vrcpps %ymm1, %ymm2
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; AVX-NEXT: vmulps %ymm2, %ymm1, %ymm1
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; AVX-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
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; AVX-NEXT: vsubps %ymm1, %ymm3, %ymm1
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; AVX-NEXT: vmulps %ymm1, %ymm2, %ymm1
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; AVX-NEXT: vaddps %ymm1, %ymm2, %ymm1
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; AVX-NEXT: vmulps %ymm1, %ymm0, %ymm0
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; AVX-NEXT: retq
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%vy = insertelement <8 x float> undef, float %y, i32 0
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