forked from OSchip/llvm-project
Organize UNPCK* patterns, also add remaining for AVX.
llvm-svn: 138519
This commit is contained in:
Bruno Cardoso Lopes
parent
9ade17b7f2
commit
fb702fe8d6
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@ -1649,6 +1649,103 @@ let AddedComplexity = 10 in {
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} // Constraints = "$src1 = $dst"
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} // AddedComplexity
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let Predicates = [HasSSE1] in {
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def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
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(UNPCKLPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
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(UNPCKLPSrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
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(UNPCKHPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
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(UNPCKHPSrr VR128:$src1, VR128:$src2)>;
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}
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let Predicates = [HasSSE2] in {
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def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
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(UNPCKLPDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
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(UNPCKLPDrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
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(UNPCKHPDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
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(UNPCKHPDrr VR128:$src1, VR128:$src2)>;
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// FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the
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// problem is during lowering, where it's not possible to recognize the load
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// fold cause it has two uses through a bitcast. One use disappears at isel
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// time and the fold opportunity reappears.
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def : Pat<(v2f64 (X86Movddup VR128:$src)),
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(UNPCKLPDrr VR128:$src, VR128:$src)>;
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let AddedComplexity = 10 in
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def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
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(UNPCKLPDrr VR128:$src, VR128:$src)>;
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}
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let Predicates = [HasAVX] in {
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def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
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(VUNPCKLPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
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(VUNPCKLPSrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
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(VUNPCKHPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
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(VUNPCKHPSrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, (memopv8f32 addr:$src2))),
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(VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
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(VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
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(VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, (memopv8i32 addr:$src2))),
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(VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, (memopv8f32 addr:$src2))),
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(VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
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(VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, (memopv8i32 addr:$src2))),
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(VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
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(VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
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(VUNPCKLPDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
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(VUNPCKLPDrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
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(VUNPCKHPDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
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(VUNPCKHPDrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, (memopv4f64 addr:$src2))),
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(VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
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(VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, (memopv4i64 addr:$src2))),
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(VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
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(VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, (memopv4f64 addr:$src2))),
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(VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
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(VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, (memopv4i64 addr:$src2))),
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(VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
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(VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
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// FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the
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// problem is during lowering, where it's not possible to recognize the load
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// fold cause it has two uses through a bitcast. One use disappears at isel
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// time and the fold opportunity reappears.
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def : Pat<(v2f64 (X86Movddup VR128:$src)),
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(VUNPCKLPDrr VR128:$src, VR128:$src)>;
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let AddedComplexity = 10 in
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def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
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(VUNPCKLPDrr VR128:$src, VR128:$src)>;
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}
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//===----------------------------------------------------------------------===//
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// SSE 1 & 2 - Extract Floating-Point Sign mask
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//===----------------------------------------------------------------------===//
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@ -4244,8 +4341,6 @@ def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
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// Splat v2f64 / v2i64
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let AddedComplexity = 10 in {
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def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
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(UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
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def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
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(PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
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}
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@ -6055,101 +6150,6 @@ def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
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// The AVX version of some but not all of them are described here, and more
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// should come in a near future.
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// Shuffle with UNPCKLPS
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def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
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(VUNPCKLPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
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(UNPCKLPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
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(VUNPCKLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
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(UNPCKLPSrr VR128:$src1, VR128:$src2)>;
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// Shuffle with VUNPCKHPSY
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def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, (memopv8f32 addr:$src2))),
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(VUNPCKLPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
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(VUNPCKLPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
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(VUNPCKLPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, (memopv8i32 addr:$src2))),
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(VUNPCKLPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
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// Shuffle with UNPCKHPS
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def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
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(VUNPCKHPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
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(UNPCKHPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
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(VUNPCKHPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
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(UNPCKHPSrr VR128:$src1, VR128:$src2)>;
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// Shuffle with VUNPCKHPSY
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def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, (memopv8f32 addr:$src2))),
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(VUNPCKHPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
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(VUNPCKHPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, (memopv8i32 addr:$src2))),
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(VUNPCKHPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
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(VUNPCKHPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
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// Shuffle with UNPCKLPD
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def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
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(VUNPCKLPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
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(UNPCKLPDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
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(VUNPCKLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
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(UNPCKLPDrr VR128:$src1, VR128:$src2)>;
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// Shuffle with VUNPCKLPDY
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def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, (memopv4f64 addr:$src2))),
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(VUNPCKLPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
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(VUNPCKLPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, (memopv4i64 addr:$src2))),
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(VUNPCKLPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
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(VUNPCKLPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
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// Shuffle with UNPCKHPD
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def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
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(VUNPCKHPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
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(UNPCKHPDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
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(VUNPCKHPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
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(UNPCKHPDrr VR128:$src1, VR128:$src2)>;
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// Shuffle with VUNPCKHPDY
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def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, (memopv4f64 addr:$src2))),
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(VUNPCKHPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
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(VUNPCKHPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, (memopv4i64 addr:$src2))),
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(VUNPCKHPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
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(VUNPCKHPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
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// FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the problem
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// is during lowering, where it's not possible to recognize the load fold cause
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// it has two uses through a bitcast. One use disappears at isel time and the
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// fold opportunity reappears.
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def : Pat<(v2f64 (X86Movddup VR128:$src)),
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(UNPCKLPDrr VR128:$src, VR128:$src)>;
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// Shuffle with MOVLHPD
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def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
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(scalar_to_vector (loadf64 addr:$src2)))),
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