maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

AMDGPU/GlobalISel: Fail select of G_INSERT non-32-bit source 

This was producing an illegal copy which would hit an assert
later. Error on selection for now until this is implemented.

llvm-svn: 371993
This commit is contained in:
Matt Arsenault 2019-09-16 14:26:14 +00:00
parent 07b8597656
commit fb51e64eac
1 changed files with 16 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
View File

@ -533,12 +533,24 @@ bool AMDGPUInstructionSelector::selectG_INSERT(MachineInstr &I) const {
MachineBasicBlock *BB = I.getParent(); MachineBasicBlock *BB = I.getParent();
MachineFunction *MF = BB->getParent(); MachineFunction *MF = BB->getParent();
MachineRegisterInfo &MRI = MF->getRegInfo(); MachineRegisterInfo &MRI = MF->getRegInfo();
unsigned SubReg = TRI.getSubRegFromChannel(I.getOperand(3).getImm() / 32);
DebugLoc DL = I.getDebugLoc(); Register Src0Reg = I.getOperand(1).getReg();
Register Src1Reg = I.getOperand(2).getReg();
LLT Src1Ty = MRI.getType(Src1Reg);
if (Src1Ty.getSizeInBits() != 32)
return false;
int64_t Offset = I.getOperand(3).getImm();
if (Offset % 32 != 0)
return false;
unsigned SubReg = TRI.getSubRegFromChannel(Offset / 32);
const DebugLoc &DL = I.getDebugLoc();
MachineInstr *Ins = BuildMI(*BB, &I, DL, TII.get(TargetOpcode::INSERT_SUBREG)) MachineInstr *Ins = BuildMI(*BB, &I, DL, TII.get(TargetOpcode::INSERT_SUBREG))
.addDef(I.getOperand(0).getReg()) .addDef(I.getOperand(0).getReg())
.addReg(I.getOperand(1).getReg()) .addReg(Src0Reg)
.addReg(I.getOperand(2).getReg()) .addReg(Src1Reg)
.addImm(SubReg); .addImm(SubReg);
for (const MachineOperand &MO : Ins->operands()) { for (const MachineOperand &MO : Ins->operands()) {