From fb51e64eaccb49199f06982f4170b160c5737420 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 16 Sep 2019 14:26:14 +0000 Subject: [PATCH] AMDGPU/GlobalISel: Fail select of G_INSERT non-32-bit source This was producing an illegal copy which would hit an assert later. Error on selection for now until this is implemented. llvm-svn: 371993 --- .../AMDGPU/AMDGPUInstructionSelector.cpp | 20 +++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index 23ca49b8a84c..217b39969961 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -533,12 +533,24 @@ bool AMDGPUInstructionSelector::selectG_INSERT(MachineInstr &I) const { MachineBasicBlock *BB = I.getParent(); MachineFunction *MF = BB->getParent(); MachineRegisterInfo &MRI = MF->getRegInfo(); - unsigned SubReg = TRI.getSubRegFromChannel(I.getOperand(3).getImm() / 32); - DebugLoc DL = I.getDebugLoc(); + + Register Src0Reg = I.getOperand(1).getReg(); + Register Src1Reg = I.getOperand(2).getReg(); + LLT Src1Ty = MRI.getType(Src1Reg); + if (Src1Ty.getSizeInBits() != 32) + return false; + + int64_t Offset = I.getOperand(3).getImm(); + if (Offset % 32 != 0) + return false; + + unsigned SubReg = TRI.getSubRegFromChannel(Offset / 32); + const DebugLoc &DL = I.getDebugLoc(); + MachineInstr *Ins = BuildMI(*BB, &I, DL, TII.get(TargetOpcode::INSERT_SUBREG)) .addDef(I.getOperand(0).getReg()) - .addReg(I.getOperand(1).getReg()) - .addReg(I.getOperand(2).getReg()) + .addReg(Src0Reg) + .addReg(Src1Reg) .addImm(SubReg); for (const MachineOperand &MO : Ins->operands()) {