forked from OSchip/llvm-project
parent
505eb498bd
commit
fb4c4178a2
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@ -2976,7 +2976,7 @@ HexagonTargetLowering::getConstraintType(StringRef Constraint) const {
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return TargetLowering::getConstraintType(Constraint);
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}
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std::pair<unsigned, const TargetRegisterClass *>
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std::pair<unsigned, const TargetRegisterClass*>
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HexagonTargetLowering::getRegForInlineAsmConstraint(
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const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
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bool UseHVX = Subtarget.useHVXOps(), UseHVXDbl = Subtarget.useHVXDblOps();
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@ -3024,7 +3024,6 @@ HexagonTargetLowering::getRegForInlineAsmConstraint(
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case MVT::v128i8:
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if (Subtarget.hasV60TOps() && UseHVX && UseHVXDbl)
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return std::make_pair(0U, &Hexagon::VectorRegs128BRegClass);
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else
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return std::make_pair(0U, &Hexagon::VecDblRegsRegClass);
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case MVT::v256i8:
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case MVT::v128i16:
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