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[Hexagon] Fix subesthetic indentation 

llvm-svn: 279303
This commit is contained in:
Krzysztof Parzyszek 2016-08-19 19:29:15 +00:00
parent 505eb498bd
commit fb4c4178a2
3 changed files with 50 additions and 51 deletions
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4
llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
View File

@ -1005,8 +1005,8 @@ void HexagonDAGToDAGISel::SelectBitOp(SDNode *N) {
if (N->getOperand(1).getOpcode() == ISD::Constant)
Val = cast<ConstantSDNode>((N)->getOperand(1))->getSExtValue();
else {
SelectCode(N);
return;
SelectCode(N);
return;
}
}

91
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@ -2976,7 +2976,7 @@ HexagonTargetLowering::getConstraintType(StringRef Constraint) const {
return TargetLowering::getConstraintType(Constraint);
}
std::pair<unsigned, const TargetRegisterClass *>
std::pair<unsigned, const TargetRegisterClass*>
HexagonTargetLowering::getRegForInlineAsmConstraint(
const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
bool UseHVX = Subtarget.useHVXOps(), UseHVXDbl = Subtarget.useHVXDblOps();
@ -2984,54 +2984,53 @@ HexagonTargetLowering::getRegForInlineAsmConstraint(
if (Constraint.size() == 1) {
switch (Constraint[0]) {
case 'r': // R0-R31
switch (VT.SimpleTy) {
default:
llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
case MVT::i1:
case MVT::i8:
case MVT::i16:
case MVT::i32:
case MVT::f32:
return std::make_pair(0U, &Hexagon::IntRegsRegClass);
case MVT::i64:
case MVT::f64:
return std::make_pair(0U, &Hexagon::DoubleRegsRegClass);
switch (VT.SimpleTy) {
default:
llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
case MVT::i1:
case MVT::i8:
case MVT::i16:
case MVT::i32:
case MVT::f32:
return std::make_pair(0U, &Hexagon::IntRegsRegClass);
case MVT::i64:
case MVT::f64:
return std::make_pair(0U, &Hexagon::DoubleRegsRegClass);
}
case 'q': // q0-q3
switch (VT.SimpleTy) {
default:
llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
case MVT::v1024i1:
case MVT::v512i1:
case MVT::v32i16:
case MVT::v16i32:
case MVT::v64i8:
case MVT::v8i64:
return std::make_pair(0U, &Hexagon::VecPredRegsRegClass);
}
switch (VT.SimpleTy) {
default:
llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
case MVT::v1024i1:
case MVT::v512i1:
case MVT::v32i16:
case MVT::v16i32:
case MVT::v64i8:
case MVT::v8i64:
return std::make_pair(0U, &Hexagon::VecPredRegsRegClass);
}
case 'v': // V0-V31
switch (VT.SimpleTy) {
default:
llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
case MVT::v16i32:
case MVT::v32i16:
case MVT::v64i8:
case MVT::v8i64:
return std::make_pair(0U, &Hexagon::VectorRegsRegClass);
case MVT::v32i32:
case MVT::v64i16:
case MVT::v16i64:
case MVT::v128i8:
if (Subtarget.hasV60TOps() && UseHVX && UseHVXDbl)
return std::make_pair(0U, &Hexagon::VectorRegs128BRegClass);
else
return std::make_pair(0U, &Hexagon::VecDblRegsRegClass);
case MVT::v256i8:
case MVT::v128i16:
case MVT::v64i32:
case MVT::v32i64:
return std::make_pair(0U, &Hexagon::VecDblRegs128BRegClass);
}
switch (VT.SimpleTy) {
default:
llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
case MVT::v16i32:
case MVT::v32i16:
case MVT::v64i8:
case MVT::v8i64:
return std::make_pair(0U, &Hexagon::VectorRegsRegClass);
case MVT::v32i32:
case MVT::v64i16:
case MVT::v16i64:
case MVT::v128i8:
if (Subtarget.hasV60TOps() && UseHVX && UseHVXDbl)
return std::make_pair(0U, &Hexagon::VectorRegs128BRegClass);
return std::make_pair(0U, &Hexagon::VecDblRegsRegClass);
case MVT::v256i8:
case MVT::v128i16:
case MVT::v64i32:
case MVT::v32i64:
return std::make_pair(0U, &Hexagon::VecDblRegs128BRegClass);
}
default:
llvm_unreachable("Unknown asm register class");

6
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
View File

@ -3736,7 +3736,7 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup(
(Hexagon::P0 == SrcReg)) &&
(Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
return HexagonII::HSIG_L2;
break;
break;
case Hexagon::L4_return_t :
case Hexagon::L4_return_f :
case Hexagon::L4_return_tnew_pnt :
@ -4104,8 +4104,8 @@ bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond,
return false;
assert(Cond.size() == 2);
if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
return false;
DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
return false;
}
PredReg = Cond[1].getReg();
PredRegPos = 1;