[AMDGPU] NFC target dependent requiresUniformRegister refactored out

Summary: Target specific method encapsulated into the Target Lowering Info.

Reviewers: rampitec, vpykhtin

Reviewed By: rampitec

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70085

llvm/include/llvm/CodeGen/TargetLowering.h

@@ -28,6 +28,7 @@
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
+#include "llvm/Analysis/LegacyDivergenceAnalysis.h"
 #include "llvm/CodeGen/DAGCombine.h"
 #include "llvm/CodeGen/ISDOpcodes.h"
 #include "llvm/CodeGen/RuntimeLibcalls.h"
@@ -821,12 +822,12 @@ public:
     return RC;
   }
 
-  /// Allows target to decide about the register class of the
+  /// Allows target to decide about the divergence of the
-  /// specific value that is live outside the defining block.
+  /// specific value. Base class implementation returns true
-  /// Returns true if the value needs uniform register class.
+  /// if the Divergece Analysis exists and reports value as divergent.
-  virtual bool requiresUniformRegister(MachineFunction &MF,
+  virtual bool isDivergent(const LegacyDivergenceAnalysis *DA,
-                                       const Value *) const {
+                           MachineFunction &MF, const Value *V) const {
-    return false;
+    return DA && DA->isDivergent(V);
   }
 
   /// Return the 'representative' register class for the specified value

llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp

@@ -398,8 +398,7 @@ Register FunctionLoweringInfo::CreateRegs(Type *Ty, bool isDivergent) {
 }
 
 Register FunctionLoweringInfo::CreateRegs(const Value *V) {
-  return CreateRegs(V->getType(), DA && DA->isDivergent(V) &&
+  return CreateRegs(V->getType(), TLI->isDivergent(DA, *MF, V));
-                    !TLI->requiresUniformRegister(*MF, V));
 }
 
 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

@@ -11226,6 +11226,12 @@ SITargetLowering::getRegClassFor(MVT VT, bool isDivergent) const {
   return RC;
 }
 
+bool SITargetLowering::isDivergent(const LegacyDivergenceAnalysis *DA,
+                                   MachineFunction &MF, const Value *V) const {
+  return !requiresUniformRegister(MF, V) &&
+         TargetLoweringBase::isDivergent(DA, MF, V);
+}
+
 // FIXME: This is a workaround for DivergenceAnalysis not understanding always
 // uniform values (as produced by the mask results of control flow intrinsics)
 // used outside of divergent blocks. The phi users need to also be treated as

llvm/lib/Target/AMDGPU/SIISelLowering.h

@@ -416,8 +416,9 @@ public:
 
   virtual const TargetRegisterClass *
   getRegClassFor(MVT VT, bool isDivergent) const override;
-  virtual bool requiresUniformRegister(MachineFunction &MF,
+  virtual bool isDivergent(const LegacyDivergenceAnalysis *DA,
-                                       const Value *V) const override;
+                           MachineFunction &MF, const Value *V) const override;
+  bool requiresUniformRegister(MachineFunction &MF, const Value *V) const;
   Align getPrefLoopAlignment(MachineLoop *ML) const override;
 
   void allocateHSAUserSGPRs(CCState &CCInfo,